[
  {
    "namespace": "alex-forencich",
    "name": "verilog-ethernet",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Verilog Ethernet MAC + IP/UDP stack supporting 1G/10G/25G/40G/100G with both Intel and Xilinx primitives (Alex Forencich). Deprecated upstream \u2014 author moved active development to fpganinja/taxi (CERN-OHL-S-2.0).",
    "license": "MIT",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/alexforencich/verilog-ethernet.git",
    "tags": [
      "arbitration",
      "controller",
      "deinterleave",
      "demultiplexer",
      "independent",
      "interface",
      "interleave",
      "multiplexer",
      "resolution",
      "synchronizer",
      "synchronous",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T22:57:14Z",
    "updated_at": "2025-02-27T15:50:25-08:00",
    "status": "deprecated-upstream",
    "successor": "fpganinja/taxi",
    "health_tier": "silver",
    "contract_url": "https://github.com/routertl/ip-index/blob/main/contracts/eth_mac_1g_requirements.yml",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "contract": {
      "traits": {
        "rx_strips_fcs": true,
        "tx_user_frame_includes_fcs": false
      },
      "defects": []
    },
    "top_ports": {
      "axis_eth_fcs": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_fcs",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "output_fcs_valid",
          "type": "wire",
          "width": ""
        }
      ],
      "axis_eth_fcs_check": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "axis_eth_fcs_check_64": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "axis_eth_fcs_insert": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "axis_eth_fcs_insert_64": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "k",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_axis_rx": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "error_header_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_axis_tx": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "AXI",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_demux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_hdr_valid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_eth_hdr_ready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[M_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[M_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_eth_payload_axis_tready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tlast",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tid",
          "type": "wire",
          "width": "[M_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdest",
          "type": "wire",
          "width": "[M_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tuser",
          "type": "wire",
          "width": "[M_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "drop",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(M_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_10g_fifo": [
        {
          "direction": "in",
          "name": "rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": "[TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_96",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PTP_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tx_ptp_ts_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": "[RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "xgmii_rxd",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "xgmii_rxc",
          "type": "wire",
          "width": "[CTRL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "xgmii_txd",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "xgmii_txc",
          "type": "wire",
          "width": "[CTRL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_ts_96",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_ts_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_1g_fifo": [
        {
          "direction": "in",
          "name": "rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_rxd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "gmii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_txd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "gmii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_mii_select",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_mii_select",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_1g_gmii_fifo": [
        {
          "direction": "in",
          "name": "style",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gtx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gtx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_rxd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "gmii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_txd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "gmii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "speed",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_1g_rgmii_fifo": [
        {
          "direction": "in",
          "name": "style",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gtx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gtx_clk90",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gtx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rgmii_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rgmii_rxd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "rgmii_rx_ctl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rgmii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rgmii_txd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "rgmii_tx_ctl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "speed",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_mii_fifo": [
        {
          "direction": "in",
          "name": "style",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rxd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "mii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_txd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "mii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mac_phy_10g_fifo": [
        {
          "direction": "in",
          "name": "rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_axis_tuser",
          "type": "wire",
          "width": "[TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_96",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PTP_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_ptp_ts_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tx_ptp_ts_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tdata",
          "type": "wire",
          "width": "[AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tkeep",
          "type": "wire",
          "width": "[AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_axis_tuser",
          "type": "wire",
          "width": "[RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_tx_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_tx_hdr",
          "type": "wire",
          "width": "[HDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "serdes_rx_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "serdes_rx_hdr",
          "type": "wire",
          "width": "[HDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_rx_bitslip",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "serdes_rx_reset_req",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_error_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_bad_fcs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_bad_block",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_block_lock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_high_ber",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_status",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_bad_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_fifo_good_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_ts_96",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_ts_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_ifg",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "cfg_tx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_tx_prbs31_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_prbs31_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_mux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_hdr_valid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_eth_hdr_ready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[S_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[S_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tvalid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_eth_payload_axis_tready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tlast",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tid",
          "type": "wire",
          "width": "[S_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdest",
          "type": "wire",
          "width": "[S_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tuser",
          "type": "wire",
          "width": "[S_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(S_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "eth_phy_10g": [
        {
          "direction": "in",
          "name": "rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "xgmii_txd",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "xgmii_txc",
          "type": "wire",
          "width": "[CTRL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "xgmii_rxd",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "xgmii_rxc",
          "type": "wire",
          "width": "[CTRL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_tx_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_tx_hdr",
          "type": "wire",
          "width": "[HDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "serdes_rx_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "serdes_rx_hdr",
          "type": "wire",
          "width": "[HDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "serdes_rx_bitslip",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "serdes_rx_reset_req",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_bad_block",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_error_count",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "out",
          "name": "rx_bad_block",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_sequence_error",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_block_lock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_high_ber",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_status",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_tx_prbs31_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_rx_prbs31_enable",
          "type": "wire",
          "width": ""
        }
      ],
      "ip_demux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_hdr_valid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_ip_hdr_ready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[M_COUNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[M_COUNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[M_COUNT*6-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[M_COUNT*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[M_COUNT*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[M_COUNT*13-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[M_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[M_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[M_COUNT*32-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[M_COUNT*32-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[M_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[M_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_ip_payload_axis_tready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tlast",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tid",
          "type": "wire",
          "width": "[M_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdest",
          "type": "wire",
          "width": "[M_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tuser",
          "type": "wire",
          "width": "[M_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "drop",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(M_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "ip_mux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_hdr_valid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_ip_hdr_ready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_version",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ihl",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[S_COUNT*6-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[S_COUNT*2-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_identification",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_flags",
          "type": "wire",
          "width": "[S_COUNT*3-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_fragment_offset",
          "type": "wire",
          "width": "[S_COUNT*13-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_header_checksum",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[S_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[S_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tvalid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_ip_payload_axis_tready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tlast",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tid",
          "type": "wire",
          "width": "[S_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdest",
          "type": "wire",
          "width": "[S_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tuser",
          "type": "wire",
          "width": "[S_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(S_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_clock": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_96",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_96_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_64",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_64_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_period_ns",
          "type": "wire",
          "width": "[PERIOD_NS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_period_fns",
          "type": "wire",
          "width": "[FNS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_period_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_adj_ns",
          "type": "wire",
          "width": "[OFFSET_NS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_adj_fns",
          "type": "wire",
          "width": "[FNS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_adj_count",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "input_adj_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_adj_active",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_drift_ns",
          "type": "wire",
          "width": "[DRIFT_NS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_drift_fns",
          "type": "wire",
          "width": "[FNS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_drift_rate",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "input_drift_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_ts_96",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_64",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pps",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_perout": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "from",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_96",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_start",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "in",
          "name": "input_start_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_period",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "in",
          "name": "input_period_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_width",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "in",
          "name": "input_width_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "error",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pulse",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_tag_insert": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tag",
          "type": "wire",
          "width": "[TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tag_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tag_ready",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_td_leaf": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_td_sdi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_ts_rel",
          "type": "wire",
          "width": "[TS_REL_W-1:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_rel_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_ts_tod",
          "type": "wire",
          "width": "[TS_TOD_W-1:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_tod_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "path",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "case",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stepped",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_td_phc": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_tod_s",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_tod_ns",
          "type": "wire",
          "width": "[29:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_tod_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_ts_tod_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_tod_offset_ns",
          "type": "wire",
          "width": "[29:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_tod_offset_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_ts_tod_offset_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_rel_ns",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_rel_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_ts_rel_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_rel_offset_ns",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_rel_offset_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_ts_rel_offset_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_offset_fns",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_offset_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_ts_offset_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_period_ns",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "input_period_fns",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "input_period_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_period_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_drift_num",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "input_drift_denom",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "input_drift_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input_drift_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_td_sdo",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_pps_str",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_td_rel2tod": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_td_sdi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_ts_rel",
          "type": "wire",
          "width": "[TS_REL_W-1:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_tag",
          "type": "wire",
          "width": "[TS_TAG_W-1:0]"
        },
        {
          "direction": "in",
          "name": "input_ts_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_ts_tod",
          "type": "wire",
          "width": "[TS_TOD_W-1:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_tag",
          "type": "wire",
          "width": "[TS_TAG_W-1:0]"
        },
        {
          "direction": "out",
          "name": "output_ts_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "path",
          "type": "wire",
          "width": ""
        }
      ],
      "ptp_ts_extract": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ts",
          "type": "wire",
          "width": "[TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ts_valid",
          "type": "wire",
          "width": ""
        }
      ],
      "ssio_ddr_in_diff": [
        {
          "direction": "in",
          "name": "style",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_d_p",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_d_n",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_q1",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_q2",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        }
      ],
      "ssio_ddr_out_diff": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk90",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_d1",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_d2",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_q_p",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_q_n",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        }
      ],
      "ssio_sdr_in_diff": [
        {
          "direction": "in",
          "name": "style",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_d_p",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "input_d_n",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_q",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        }
      ],
      "ssio_sdr_out_diff": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_d",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_q_p",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "output_q_n",
          "type": "wire",
          "width": "[WIDTH-1:0]"
        }
      ],
      "udp_arb_mux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_hdr_valid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_udp_hdr_ready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_version",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ihl",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[S_COUNT*6-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[S_COUNT*2-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_identification",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_flags",
          "type": "wire",
          "width": "[S_COUNT*3-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_fragment_offset",
          "type": "wire",
          "width": "[S_COUNT*13-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_header_checksum",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_source_port",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_dest_port",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_length",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_checksum",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[S_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[S_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tvalid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_udp_payload_axis_tready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tlast",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tid",
          "type": "wire",
          "width": "[S_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[S_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[S_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "udp_complete": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_tx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_header_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_invalid_header",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_invalid_checksum",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_error_arp_failed",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_error_header_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_tx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "local_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "local_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "gateway_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "subnet_mask",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clear_arp_cache",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "classifier",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "assign",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "arbiter",
          "type": "wire",
          "width": ""
        }
      ],
      "udp_complete_64": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_eth_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_ip_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_ip_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_ip_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tuser",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_tx_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_header_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_invalid_header",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_rx_error_invalid_checksum",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ip_tx_error_arp_failed",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_error_header_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_rx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "udp_tx_error_payload_early_termination",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "local_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "local_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "gateway_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "subnet_mask",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clear_arp_cache",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "classifier",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "assign",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "arbiter",
          "type": "wire",
          "width": ""
        }
      ],
      "udp_demux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_hdr_valid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_udp_hdr_ready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[M_COUNT*48-1:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[M_COUNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[M_COUNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[M_COUNT*6-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[M_COUNT*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[M_COUNT*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[M_COUNT*13-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[M_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[M_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[M_COUNT*32-1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[M_COUNT*32-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_source_port",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_dest_port",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_length",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_checksum",
          "type": "wire",
          "width": "[M_COUNT*16-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[M_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[M_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_udp_payload_axis_tready",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tlast",
          "type": "wire",
          "width": "[M_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tid",
          "type": "wire",
          "width": "[M_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[M_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[M_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "drop",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(M_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "udp_mux": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_udp_hdr_valid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_udp_hdr_ready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_dest_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_src_mac",
          "type": "wire",
          "width": "[S_COUNT*48-1:0]"
        },
        {
          "direction": "in",
          "name": "s_eth_type",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_version",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ihl",
          "type": "wire",
          "width": "[S_COUNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dscp",
          "type": "wire",
          "width": "[S_COUNT*6-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ecn",
          "type": "wire",
          "width": "[S_COUNT*2-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_length",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_identification",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_flags",
          "type": "wire",
          "width": "[S_COUNT*3-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_fragment_offset",
          "type": "wire",
          "width": "[S_COUNT*13-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_ttl",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_protocol",
          "type": "wire",
          "width": "[S_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_header_checksum",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_source_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_ip_dest_ip",
          "type": "wire",
          "width": "[S_COUNT*32-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_source_port",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_dest_port",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_length",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_checksum",
          "type": "wire",
          "width": "[S_COUNT*16-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[S_COUNT*DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[S_COUNT*KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tvalid",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_udp_payload_axis_tready",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tlast",
          "type": "wire",
          "width": "[S_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tid",
          "type": "wire",
          "width": "[S_COUNT*ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[S_COUNT*DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[S_COUNT*USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_hdr_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_hdr_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_eth_dest_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_src_mac",
          "type": "wire",
          "width": "[47:0]"
        },
        {
          "direction": "out",
          "name": "m_eth_type",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_version",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ihl",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dscp",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ecn",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_identification",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_flags",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_fragment_offset",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_ttl",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_protocol",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_header_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_source_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_ip_dest_ip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_source_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_dest_port",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_length",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_checksum",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdata",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tkeep",
          "type": "wire",
          "width": "[KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_udp_payload_axis_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tid",
          "type": "wire",
          "width": "[ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tdest",
          "type": "wire",
          "width": "[DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tuser",
          "type": "wire",
          "width": "[USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "select",
          "type": "wire",
          "width": "[$clog2(S_COUNT)-1:0]"
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_udp_payload_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        }
      ],
      "xgmii_deinterleave": [
        {
          "direction": "in",
          "name": "input_xgmii_dc",
          "type": "wire",
          "width": "[72:0]"
        },
        {
          "direction": "out",
          "name": "output_xgmii_d",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "output_xgmii_c",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "xgmii_interleave": [
        {
          "direction": "in",
          "name": "input_xgmii_d",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "input_xgmii_c",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "output_xgmii_dc",
          "type": "wire",
          "width": "[72:0]"
        }
      ]
    },
    "top_modules": [
      "axis_eth_fcs",
      "axis_eth_fcs_check",
      "axis_eth_fcs_check_64",
      "axis_eth_fcs_insert",
      "axis_eth_fcs_insert_64",
      "eth_axis_rx",
      "eth_axis_tx",
      "eth_demux",
      "eth_mac_10g_fifo",
      "eth_mac_1g_fifo",
      "eth_mac_1g_gmii_fifo",
      "eth_mac_1g_rgmii_fifo",
      "eth_mac_mii_fifo",
      "eth_mac_phy_10g_fifo",
      "eth_mux",
      "eth_phy_10g",
      "ip_demux",
      "ip_mux",
      "ptp_clock",
      "ptp_perout",
      "ptp_tag_insert",
      "ptp_td_leaf",
      "ptp_td_phc",
      "ptp_td_rel2tod",
      "ptp_ts_extract",
      "ssio_ddr_in_diff",
      "ssio_ddr_out_diff",
      "ssio_sdr_in_diff",
      "ssio_sdr_out_diff",
      "udp_arb_mux",
      "udp_complete",
      "udp_complete_64",
      "udp_demux",
      "udp_mux",
      "xgmii_deinterleave",
      "xgmii_interleave"
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad408x_phy",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Ad408x IP core with ready/valid handshake and configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad408x",
      "layer",
      "phy",
      "physical"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad463x_data_capture",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Ad463x IP core with ready/valid handshake and configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad463x",
      "capture",
      "data"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad463x_data_capture": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "echo_sclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_in",
          "type": "wire",
          "width": "[NUM_OF_LANES-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data",
          "type": "wire",
          "width": "[(NUM_OF_LANES * DATA_WIDTH)-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "assign",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad9265_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI interface controller for the AD9265 analog-to-digital converter.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad9265",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad9265_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad9434_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Drives SPI communication.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad9434",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad9434_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad9467_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Interfaces with an AD9467 analog-to-digital converter via SPI protocol for configuration and readback operations.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad9467",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad9467_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad_adl5904_rst",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates reset signal.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "adl5904",
      "reset",
      "rst"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad_adl5904_rst": [
        {
          "direction": "in",
          "name": "sys_cpu_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rf_peak_det_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rf_peak_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "protection",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad_bus_mux",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Multiplexer with configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "bus",
      "multiplexer",
      "mux"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ad_bus_mux": [
        {
          "direction": "in",
          "name": "select_path",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_in_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_in_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_in_0",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "valid_in_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_in_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_in_1",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "valid_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "enable_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_out",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ad_csc_CrYCb2RGB",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Converts CrYCb to RGB.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "crycb2rgb",
      "csc"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad_csc_RGB2CrYCb",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Converts RGB to CrYCb.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "csc",
      "rgb2crycb"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad_dds",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates DDS output signals.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "dds"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad_dds_1",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates DDS output data.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "dds"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ad_dds_2",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates digital signal.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad",
      "dds"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
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    "latest": "3dc381cf791c",
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        "package": "pl330_dma_fifo"
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    ]
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    "namespace": "analog-devices",
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    ]
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    "namespace": "analog-devices",
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    "role": "top",
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        "library": "work",
        "package": "pl330_dma_fifo"
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    ],
    "top_ports": {
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        {
          "direction": "in",
          "name": "link_clk",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "link_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "link_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[NUM_LANES*8*OCTETS_PER_BEAT-1:0]"
        },
        {
          "direction": "out",
          "name": "enable",
          "type": "wire",
          "width": "[NUM_CHANNELS-1:0]"
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        {
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          "width": "[NUM_CHANNELS-1:0]"
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        {
          "direction": "in",
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          "width": "[DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0]"
        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_sync_manual_req_in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[12:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
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        {
          "direction": "in",
          "name": "rx_phy_kchar_1",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_3",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_4",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_5",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_6",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_locked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_cal_busy_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_valid_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_data_7",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_disperr_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_deterr_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_kchar_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "rx_phy_full_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_phy_empty_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_align_en_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_polarity_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_lane_powerdown_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_bit_reversal_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_byte_reversal_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_analogreset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_phy_digitalreset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_core_analogreset",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "in",
          "name": "rx_core_digitalreset",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "out",
          "name": "rx_core_locked",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "out",
          "name": "rx_core_cal_busy",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "out",
          "name": "tx_ip_cal_busy",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "out",
          "name": "tx_ip_full",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "out",
          "name": "tx_ip_empty",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_data",
          "type": "wire",
          "width": "[((NUM_OF_LANES*32)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_kchar",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 4)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_elecidle",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_lane_polarity",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_lane_powerdown",
          "type": "wire",
          "width": "[((NUM_OF_LANES* 1)-1):0]"
        },
        {
          "direction": "in",
          "name": "tx_ip_bit_reversal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_ip_byte_reversal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_cal_busy_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_full_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_empty_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_data_0",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_kchar_0",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_elecidle_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_polarity_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_powerdown_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_bit_reversal_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_byte_reversal_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_analogreset_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_digitalreset_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_cal_busy_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_full_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_empty_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_data_1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_kchar_1",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_elecidle_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_polarity_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_powerdown_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_bit_reversal_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_byte_reversal_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_analogreset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_digitalreset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_cal_busy_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_full_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_empty_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_data_2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_kchar_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "tx_phy_elecidle_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_polarity_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_lane_powerdown_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_bit_reversal_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_byte_reversal_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_analogreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_phy_digitalreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_cal_busy_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_full_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_phy_empty_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
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          "width": "[ 2:0]"
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
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          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ 1:0]"
        },
        {
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          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
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          "name": "s_axi_rready",
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          "width": ""
        }
      ]
    }
  },
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    "namespace": "analog-devices",
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        "library": "work",
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      "1336749ccfa9",
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    "license_class": "permissive",
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      "amba",
      "axi",
      "bus"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
        "library": "work",
        "package": "axi_ctrlif"
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      {
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
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      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
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          "direction": "in",
          "name": "dclk_in_p",
          "type": "wire",
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        },
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          "direction": "in",
          "name": "dclk_in_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_a_in_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_a_in_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_b_in_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_b_in_n",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "cnv_in_p",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "cnv_in_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "filter_data_ready_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_data",
          "type": "wire",
          "width": "[((ADC_N_BITS > 16)? 31 : 15):0]"
        },
        {
          "direction": "out",
          "name": "adc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adc_dovf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "delay_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_ad485x",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite interface controller for AD485x high-speed analog-to-digital converter with configurable LVDS/CMOS lanes and timing control.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
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      "amba",
      "axi",
      "bus"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
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        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
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          "direction": "in",
          "name": "delay_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "external_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "external_fast_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cnvs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lvds_cmos_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lane_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
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          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
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          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "width": "[15:0]"
        },
        {
          "direction": "in",
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adc_dovf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_data_0",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_1",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_2",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_3",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_4",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_5",
          "type": "wire",
          "width": "[DW:0]"
        },
        {
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          "width": ""
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          "direction": "in",
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          "type": "wire",
          "width": ""
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          "direction": "in",
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          "width": ""
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          "direction": "in",
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          "width": "[15:0]"
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        {
          "direction": "in",
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          "width": "[ 2:0]"
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        {
          "direction": "out",
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          "width": ""
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          "direction": "in",
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          "type": "wire",
          "width": ""
        },
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          "direction": "in",
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          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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          "direction": "out",
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        },
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          "direction": "out",
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          "name": "adc_data_5",
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        },
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          "direction": "out",
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        },
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        },
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          "direction": "out",
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        },
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          "direction": "out",
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        },
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          "direction": "out",
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          "direction": "in",
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          "direction": "in",
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          "width": "[ 3:0]"
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          "direction": "out",
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        },
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          "width": ""
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          "direction": "out",
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          "name": "s_axi_bready",
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          "width": ""
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          "direction": "in",
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          "width": "[15:0]"
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          "direction": "in",
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          "width": "[ 2:0]"
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          "direction": "out",
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          "width": ""
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          "direction": "out",
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          "width": ""
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          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "s_axi_rdata",
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          "width": "[31:0]"
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        {
          "direction": "in",
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          "width": ""
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          "direction": "out",
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          "direction": "out",
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          "name": "adc_dovf",
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          "width": ""
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          "direction": "out",
          "name": "adc_data_0",
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          "width": "[15:0]"
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          "direction": "out",
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          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "adc_data_5",
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        {
          "direction": "out",
          "name": "adc_data_6",
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          "width": "[15:0]"
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "adc_data_8",
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        {
          "direction": "out",
          "name": "adc_data_9",
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          "width": "[15:0]"
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        {
          "direction": "out",
          "name": "adc_data_10",
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          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_11",
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          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_12",
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          "width": "[15:0]"
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        {
          "direction": "out",
          "name": "adc_data_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_data_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
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          "width": "[15:0]"
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          "direction": "out",
          "name": "adc_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_enable_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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        },
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          "direction": "out",
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          "width": ""
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    }
  },
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        }
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
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      {
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        },
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        {
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        },
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        {
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        {
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        {
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    "role": "top",
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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    ],
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        },
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        {
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        {
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        {
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        {
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        {
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        },
        {
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        {
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        {
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        {
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        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
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        "library": "work",
        "package": "fifo_synchronizer"
      },
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        "library": "work",
        "package": "i2s_clkgen"
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        "library": "work",
        "package": "i2s_controller"
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      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
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        "library": "work",
        "package": "pl330_dma_fifo"
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    ],
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          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trigger_in",
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        },
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          "direction": "in",
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          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "trigger_o",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "trigger_t",
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          "width": "[ 1:0]"
        },
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          "direction": "in",
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          "type": "wire",
          "width": "[15:0]"
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        {
          "direction": "in",
          "name": "data_b",
          "type": "wire",
          "width": "[15:0]"
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          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_valid_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_a_trig",
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          "width": "[15:0]"
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        {
          "direction": "out",
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          "width": "[15:0]"
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          "width": ""
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        {
          "direction": "out",
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          "direction": "out",
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          "direction": "out",
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          "direction": "out",
          "name": "fifo_depth",
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          "width": "[31:0]"
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          "direction": "in",
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        },
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          "direction": "in",
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          "width": ""
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          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[ 6:0]"
        },
        {
          "direction": "in",
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          "width": "[ 2:0]"
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        {
          "direction": "in",
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          "direction": "in",
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          "width": "[31:0]"
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          "direction": "out",
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          "direction": "out",
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        {
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        },
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        {
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        },
        {
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        }
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      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "axi_adrv9001",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite interface for ADRV9001 RF transceiver with configurable dual-channel RX/TX SSI data paths and synchronization.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "adrv9001",
      "amba",
      "axi",
      "bus"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_adrv9001": [
        {
          "direction": "in",
          "name": "mssi_sync_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ref_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mcs_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mcs_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mcs_src",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_output_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_dclk_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_dclk_in_p_dclk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_idata_in_n_idata0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_idata_in_p_idata1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_qdata_in_n_qdata2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_qdata_in_p_qdata3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_strobe_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx1_strobe_in_p_strobe_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_dclk_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_dclk_in_p_dclk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_idata_in_n_idata0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_idata_in_p_idata1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_qdata_in_n_qdata2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_qdata_in_p_qdata3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_strobe_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx2_strobe_in_p_strobe_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_dclk_out_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_dclk_out_p_dclk_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx1_dclk_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx1_dclk_in_p_dclk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_idata_out_n_idata0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_idata_out_p_idata1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_qdata_out_n_qdata2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_qdata_out_p_qdata3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_strobe_out_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_strobe_out_p_strobe_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_dclk_out_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_dclk_out_p_dclk_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx2_dclk_in_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx2_dclk_in_p_dclk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_idata_out_n_idata0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_idata_out_p_idata1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_qdata_out_n_qdata2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_qdata_out_p_qdata3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_strobe_out_n_NC",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_strobe_out_p_strobe_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx1_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx2_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx1_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx2_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "delay_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_valid_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_enable_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_data_i0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_1_valid_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_enable_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_data_q0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_1_valid_i1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_enable_i1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_data_i1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_1_valid_q1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_enable_q1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_data_q1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "adc_1_dovf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_1_start_sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_valid_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_enable_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_data_i0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "adc_2_valid_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_enable_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_data_q0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "adc_2_dovf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_2_start_sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_valid_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_enable_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_1_data_i0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_1_valid_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_enable_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_1_data_q0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_1_valid_i1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_enable_i1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_1_data_i1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_1_valid_q1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_1_enable_q1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_1_data_q1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "dac_1_dunf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_2_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_2_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_2_valid_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_2_enable_i0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_2_data_i0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_2_valid_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_2_enable_q0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_2_data_q0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "dac_2_dunf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tdd_sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tdd_sync_cntr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_rx1_enable_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_rx2_enable_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_tx1_enable_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_tx2_enable_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_adrv9001_core",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI-controlled RF transceiver interface for the ADRV9001 dual-channel radio with configurable clock, DDS, and TDD support.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "adrv9001",
      "amba",
      "axi",
      "bus",
      "core"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "axi_adrv9001_if",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Interfaces with ADRV9001 device.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "adrv9001",
      "amba",
      "axi",
      "bus"
    ],
    "role": "component",
    "library_deps": [],
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        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_1",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_1",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_2",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_2",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_3",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_3",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_5",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_5",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_6",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_6",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_7",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_7",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_8",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_9",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_9",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_9",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_10",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_10",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_10",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_11",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_11",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_11",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_12",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_13",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_13",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_13",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_14",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_14",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_14",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_15",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_15",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_15",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_16",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_17",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_17",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_17",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_18",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_18",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_18",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_19",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_19",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_19",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_20",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_21",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_21",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_21",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_22",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_22",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_22",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_23",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_23",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_23",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_24",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_25",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_25",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_25",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_26",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_26",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_26",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_27",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_27",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_27",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_cm_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_28",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_29",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_29",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_29",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_30",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_30",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_30",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_enb_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_addr_31",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_es_wr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_reset_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_es_wdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_rdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_es_ready_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_pll_locked_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rst_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_user_ready_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_rst_done_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbsforceerr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_prbssel_31",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_prbscntreset_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbserr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_prbslocked_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_ch_bufstatus_31",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_bufstatus_rst_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_lpm_dfe_n_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_rate_31",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_sys_clk_sel_31",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_out_clk_sel_31",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_diffctrl_31",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_postcursor_31",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_tx_precursor_31",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_enb_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_addr_31",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "up_ch_wr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_ch_wdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_rdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "up_ch_ready_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_status",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_pll_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
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        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "m_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_awaddr",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "m_axi_bvalid",
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        },
        {
          "direction": "in",
          "name": "m_axi_bresp",
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        {
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        {
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        {
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_rready",
          "type": "wire",
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        }
      ]
    }
  },
  {
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        {
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        },
        {
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        {
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        },
        {
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        },
        {
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        {
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        },
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        },
        {
          "direction": "in",
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          "type": "wire",
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        }
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  },
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      "HEAD",
      "1336749ccfa9",
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      "monitor"
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    "library_deps": [],
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "package": "i2s_tx"
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      {
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      }
    ],
    "top_ports": {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_1",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "clock_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
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          "width": "[ 2:0]"
        },
        {
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        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_ctrlif",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
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    "description": "AXI4-Lite controller with memory interface and configurable parameters",
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    "license_class": "permissive",
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    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
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      "ctrlif"
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
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        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
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      {
        "library": "work",
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        "library": "work",
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        "library": "work",
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        "library": "work",
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      {
        "library": "work",
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        "package": "i2s_tx"
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        "library": "work",
        "package": "pl330_dma_fifo"
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          "direction": "in",
          "name": "s_axi_aclk",
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        },
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          "direction": "in",
          "name": "s_axi_aresetn",
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          "direction": "in",
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          "direction": "in",
          "name": "s_axi_awvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
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          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
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        {
          "direction": "in",
          "name": "s_axi_wstrb",
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          "width": "(C_S_AXI_DATA_WIDTH/8)-1 downto 0"
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        {
          "direction": "in",
          "name": "s_axi_wvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "std_logic",
          "width": ""
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        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "std_logic_vector",
          "width": "C_S_AXI_ADDR_WIDTH-1 downto 0"
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        {
          "direction": "in",
          "name": "s_axi_arvalid",
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          "width": ""
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        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "std_logic",
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        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "std_logic",
          "width": ""
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        {
          "direction": "out",
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          "type": "std_logic_vector",
          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
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        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "width": ""
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        {
          "direction": "out",
          "name": "s_axi_wready",
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        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_addr",
          "type": "integer",
          "width": "0 to C_NUM_REG - 1"
        },
        {
          "direction": "in",
          "name": "rd_data",
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          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
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        {
          "direction": "out",
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        {
          "direction": "in",
          "name": "rd_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_addr",
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          "width": "0 to C_NUM_REG - 1"
        },
        {
          "direction": "out",
          "name": "wr_data",
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          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
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          "direction": "in",
          "name": "wr_ack",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_stb",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
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        "library": "work",
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        "library": "work",
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        "library": "work",
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      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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          "direction": "in",
          "name": "dac_clk",
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        },
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          "direction": "in",
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        {
          "direction": "in",
          "name": "dac_data_a",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "dac_data_b",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "dac_valid_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_valid_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_valid_a",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_valid_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_ready_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_ready_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "last_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "last_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_enable_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_enable_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_int_data_a",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_int_data_b",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dac_valid_out_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_valid_out_b",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trigger_i",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "trigger_adc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trigger_la",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[ 6:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "in",
          "name": "s_axi_bready",
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          "width": ""
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        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[ 6:0]"
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        {
          "direction": "in",
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          "width": "[ 2:0]"
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        }
      ]
    }
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
  },
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
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        "library": "work",
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        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
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        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
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      {
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      {
        "library": "work",
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        "library": "work",
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      {
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      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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    ],
    "top_ports": {
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        {
          "direction": "in",
          "name": "dma_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_data",
          "type": "wire",
          "width": "[(DMA_DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "dma_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_xfer_req",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_xfer_last",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_data",
          "type": "wire",
          "width": "[(DAC_DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "dac_dunf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_xfer_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bypass",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_resetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_awid",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_awburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "axi_awlock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_awcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "axi_awqos",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_awlen",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "axi_awsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "axi_awaddr",
          "type": "wire",
          "width": "[ 31:0]"
        },
        {
          "direction": "in",
          "name": "axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_wdata",
          "type": "wire",
          "width": "[(AXI_DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "axi_wstrb",
          "type": "wire",
          "width": "[(AXI_DATA_WIDTH/8-1):0]"
        },
        {
          "direction": "out",
          "name": "axi_wlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_bid",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_arid",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_arburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "axi_arlock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi_arcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "axi_arqos",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "axi_arlen",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "axi_arsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "axi_araddr",
          "type": "wire",
          "width": "[ 31:0]"
        },
        {
          "direction": "in",
          "name": "axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_rid",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "axi_rlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi_rdata",
          "type": "wire",
          "width": "[(AXI_DATA_WIDTH-1):0]"
        },
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          "direction": "out",
          "name": "axi_rready",
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          "width": ""
        }
      ]
    }
  },
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    "namespace": "analog-devices",
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    "created_at": "2026-04-15T23:18:14Z",
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    "created_at": "2026-04-15T23:18:14Z",
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    "created_at": "2026-04-15T23:18:14Z",
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    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
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        "library": "work",
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        "library": "work",
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    "top_ports": {
      "axi_dmac": [
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          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[10:0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
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          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[10:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awaddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awlen",
          "type": "wire",
          "width": "[7-(4*DMA_AXI_PROTOCOL_DEST):0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_DEST-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_awlock",
          "type": "wire",
          "width": "[DMA_AXI_PROTOCOL_DEST:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_wdata",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_wstrb",
          "type": "wire",
          "width": "[(DMA_DATA_WIDTH_DEST/8)-1:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_wlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_wid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_DEST-1:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_bid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_DEST-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_araddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arlen",
          "type": "wire",
          "width": "[7-(4*DMA_AXI_PROTOCOL_DEST):0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_dest_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_rdata",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_DEST-1:0]"
        },
        {
          "direction": "out",
          "name": "m_dest_axi_arlock",
          "type": "wire",
          "width": "[DMA_AXI_PROTOCOL_DEST:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_rid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_DEST-1:0]"
        },
        {
          "direction": "in",
          "name": "m_dest_axi_rlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_araddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arlen",
          "type": "wire",
          "width": "[7-(4*DMA_AXI_PROTOCOL_SRC):0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_SRC-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_arlock",
          "type": "wire",
          "width": "[DMA_AXI_PROTOCOL_SRC:0]"
        },
        {
          "direction": "in",
          "name": "m_src_axi_rdata",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_SRC-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "m_src_axi_rid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_SRC-1:0]"
        },
        {
          "direction": "in",
          "name": "m_src_axi_rlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_awaddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
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        {
          "direction": "out",
          "name": "m_src_axi_awlen",
          "type": "wire",
          "width": "[7-(4*DMA_AXI_PROTOCOL_SRC):0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_awsize",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_awburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_awcache",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "m_src_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_wdata",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_SRC-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_wstrb",
          "type": "wire",
          "width": "[(DMA_DATA_WIDTH_SRC/8)-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_wlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_src_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_src_axi_awid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_SRC-1:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_awlock",
          "type": "wire",
          "width": "[DMA_AXI_PROTOCOL_SRC:0]"
        },
        {
          "direction": "out",
          "name": "m_src_axi_wid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_SRC-1:0]"
        },
        {
          "direction": "in",
          "name": "m_src_axi_bid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH_SRC-1:0]"
        },
        {
          "direction": "in",
          "name": "m_sg_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_sg_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_sg_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_sg_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_sg_axi_araddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
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        {
          "direction": "out",
          "name": "m_sg_axi_arlen",
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          "width": "[7-(4*DMA_AXI_PROTOCOL_SG):0]"
        },
        {
          "direction": "out",
          "name": "m_sg_axi_arsize",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "m_sg_axi_arburst",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "m_sg_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
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        {
          "direction": "out",
          "name": "m_sg_axi_arcache",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "m_sg_axi_arid",
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          "width": "[AXI_ID_WIDTH_SG-1:0]"
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[DMA_AXI_PROTOCOL_SG:0]"
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        {
          "direction": "in",
          "name": "m_sg_axi_rdata",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_SG-1:0]"
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        {
          "direction": "out",
          "name": "m_sg_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_sg_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_sg_axi_rresp",
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          "width": "[ 1:0]"
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        {
          "direction": "in",
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          "width": "[AXI_ID_WIDTH_SG-1:0]"
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        {
          "direction": "in",
          "name": "m_sg_axi_rlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_sg_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_sg_axi_awaddr",
          "type": "wire",
          "width": "[DMA_AXI_ADDR_WIDTH-1:0]"
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        {
          "direction": "out",
          "name": "m_sg_axi_awlen",
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          "width": "[7-(4*DMA_AXI_PROTOCOL_SG):0]"
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "m_sg_axi_awburst",
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        {
          "direction": "out",
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          "direction": "out",
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          "direction": "in",
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          "direction": "in",
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          "direction": "out",
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          "direction": "out",
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          "direction": "in",
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        {
          "direction": "out",
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        {
          "direction": "in",
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          "type": "wire",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
          "name": "s_axis_dest",
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          "width": "[DMA_AXIS_DEST_W-1:0]"
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          "direction": "in",
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          "type": "wire",
          "width": ""
        },
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          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_data",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST-1:0]"
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        {
          "direction": "out",
          "name": "m_axis_strb",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST/8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_keep",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST/8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_user",
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          "width": "[0:0]"
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "m_axis_dest",
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          "width": "[DMA_AXIS_DEST_W-1:0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "FIFO",
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          "width": ""
        },
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          "direction": "in",
          "name": "fifo_wr_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_wr_din",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_SRC-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_wr_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifo_wr_xfer_req",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "fifo_rd_en",
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          "width": ""
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          "direction": "out",
          "name": "fifo_rd_valid",
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          "width": ""
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          "direction": "out",
          "name": "fifo_rd_dout",
          "type": "wire",
          "width": "[DMA_DATA_WIDTH_DEST-1:0]"
        },
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          "direction": "out",
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        },
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          "direction": "out",
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          "width": ""
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "out",
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        {
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        {
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        },
        {
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        {
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        {
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        },
        {
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        {
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        {
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        {
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        {
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        {
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        {
          "direction": "in",
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        },
        {
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        },
        {
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        },
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        {
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        {
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        {
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        },
        {
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        {
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      ]
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        {
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          "width": "[15:0]"
        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "hdmi_dma_sof",
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        },
        {
          "direction": "out",
          "name": "hdmi_dma_de",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_dma_data",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "hdmi_dma_ovf",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "hdmi_dma_unf",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
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        },
        {
          "direction": "in",
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        },
        {
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        {
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        {
          "direction": "out",
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
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          "width": "[ 3:0]"
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        {
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        },
        {
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          "name": "s_axi_bvalid",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ 1:0]"
        },
        {
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        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
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        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
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          "type": "wire",
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        }
      ]
    }
  },
  {
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      "HEAD",
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    "description": "Receives HDMI input and generates DMA output.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "amba",
      "axi",
      "bus",
      "core",
      "hdmi",
      "receive",
      "receiver",
      "rx"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
        "package": "axi_ctrlif"
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        "package": "axi_streaming_dma_rx_fifo"
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      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
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        "library": "work",
        "package": "dma_fifo"
      },
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        "package": "fifo_synchronizer"
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        "library": "work",
        "package": "i2s_clkgen"
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        "library": "work",
        "package": "i2s_controller"
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        "package": "i2s_rx"
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        "library": "work",
        "package": "i2s_tx"
      },
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        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
  },
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    "namespace": "analog-devices",
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    "latest": "3dc381cf791c",
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    "description": "AXI4-Lite transmit engine with ready/valid handshake",
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "axi",
      "bus",
      "hdmi",
      "transmit",
      "transmitter",
      "tx"
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    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
        "library": "work",
        "package": "axi_ctrlif"
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      {
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        "package": "axi_streaming_dma_rx_fifo"
      },
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        "package": "axi_streaming_dma_tx_fifo"
      },
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        "package": "dma_fifo"
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        "library": "work",
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      },
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        "library": "work",
        "package": "i2s_clkgen"
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        "package": "i2s_controller"
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        "library": "work",
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      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
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      "axi_hdmi_tx": [
        {
          "direction": "in",
          "name": "reference_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_out_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_out_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_16_hsync",
          "type": "wire",
          "width": ""
        },
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          "direction": "out",
          "name": "hdmi_16_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_16_data_e",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_16_data",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "hdmi_16_es_data",
          "type": "wire",
          "width": "[15:0]"
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          "direction": "out",
          "name": "hdmi_24_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_24_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_24_data_e",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_24_data",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "vga_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_red",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "vga_green",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "vga_blue",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "hdmi_36_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_36_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_36_data_e",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hdmi_36_data",
          "type": "wire",
          "width": "[35:0]"
        },
        {
          "direction": "in",
          "name": "vdma_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vdma_end_of_frame",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vdma_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vdma_data",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "vdma_ready",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
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          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
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          "width": "[ 3:0]"
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        {
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        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "clock",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
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        "library": "work",
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      {
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        "library": "work",
        "package": "pl330_dma_fifo"
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          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
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        },
        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": "[(AXI_DATA_WIDTH/8)-1 : 0]"
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
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        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[1:0]"
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        {
          "direction": "out",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "s_axi_awready",
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        },
        {
          "direction": "out",
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          "width": "[1:0]"
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        {
          "direction": "out",
          "name": "s_axi_bvalid",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "hsci_pclk",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "hsci_menc_clk",
          "type": "wire",
          "width": "[7:0]"
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        {
          "direction": "out",
          "name": "hsci_mosi_data",
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          "width": "[7:0]"
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        {
          "direction": "in",
          "name": "hsci_miso_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "hsci_pll_reset",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "hsci_pll_locked",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "hsci_vtc_rdy_bsc_tx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hsci_dly_rdy_bsc_tx",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "hsci_vtc_rdy_bsc_rx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hsci_dly_rdy_bsc_rx",
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          "width": ""
        }
      ]
    }
  },
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      "1336749ccfa9",
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    "license_class": "permissive",
    "language": "vhdl-2008",
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      "amba",
      "axi",
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      "i2s"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
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        "library": "work",
        "package": "axi_ctrlif"
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
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      {
        "library": "work",
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        "library": "work",
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      {
        "library": "work",
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      {
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      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_i2s_adi": [
        {
          "direction": "in",
          "name": "data_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bclk_o",
          "type": "std_logic_vector",
          "width": "NUM_OF_CHANNEL - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "lrclk_o",
          "type": "std_logic_vector",
          "width": "NUM_OF_CHANNEL - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "sdata_o",
          "type": "std_logic_vector",
          "width": "NUM_OF_CHANNEL - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "sdata_i",
          "type": "std_logic_vector",
          "width": "NUM_OF_CHANNEL - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "dma_req_tx_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_tx_rstn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_tx_davalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_tx_datype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_tx_daready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_tx_drvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_tx_drtype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_tx_drlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_tx_drready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rx_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rx_rstn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rx_davalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rx_datype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_rx_daready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_rx_drvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_rx_drtype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_rx_drlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rx_drready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "std_logic_vector",
          "width": "S_AXI_ADDRESS_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "std_logic_vector",
          "width": "S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "std_logic_vector",
          "width": "(S_AXI_DATA_WIDTH/8)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "std_logic_vector",
          "width": "S_AXI_ADDRESS_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "std_logic_vector",
          "width": "S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_intr_monitor",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite with interrupt support",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "intr",
      "monitor"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_intr_monitor": [
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_jesd204_rx",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite receive engine with ready/valid handshake and memory interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "jesd204",
      "receive",
      "receiver",
      "rx"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_jesd204_rx": [
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "core_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "core_reset_ext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "core_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "device_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "device_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "core_cfg_lanes_disable",
          "type": "wire",
          "width": "[NUM_LANES-1:0]"
        },
        {
          "direction": "out",
          "name": "core_cfg_links_disable",
          "type": "wire",
          "width": "[NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "core_cfg_octets_per_multiframe",
          "type": "wire",
          "width": "[9:0]"
        },
        {
          "direction": "out",
          "name": "core_cfg_octets_per_frame",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "core_cfg_disable_scrambler",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "core_cfg_disable_char_replacement",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "core_cfg_frame_align_err_threshold",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "device_cfg_octets_per_multiframe",
          "type": "wire",
          "width": "[9:0]"
        },
        {
          "direction": "out",
          "name": "device_cfg_octets_per_frame",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "device_cfg_beats_per_multiframe",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "device_cfg_lmfc_offset",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "device_cfg_sysref_oneshot",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "device_cfg_sysref_disable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "device_cfg_buffer_early_release",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "device_cfg_buffer_delay",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "core_ilas_config_valid",
          "type": "wire",
          "width": "[NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_ilas_config_addr",
          "type": "wire",
          "width": "[2*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_ilas_config_data",
          "type": "wire",
          "width": "[NUM_LANES*DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "device_event_sysref_alignment_error",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "device_event_sysref_edge",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "core_event_frame_alignment_error",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "core_event_unexpected_lane_state_error",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "core_ctrl_err_statistics_mask",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "out",
          "name": "core_ctrl_err_statistics_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "core_status_err_statistics_cnt",
          "type": "wire",
          "width": "[32*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_ctrl_state",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_lane_cgs_state",
          "type": "wire",
          "width": "[2*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_lane_emb_state",
          "type": "wire",
          "width": "[3*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_lane_ifs_ready",
          "type": "wire",
          "width": "[NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_lane_latency",
          "type": "wire",
          "width": "[14*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "core_status_lane_frame_align_err_cnt",
          "type": "wire",
          "width": "[8*NUM_LANES-1:0]"
        },
        {
          "direction": "in",
          "name": "status_synth_params0",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "status_synth_params1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "status_synth_params2",
          "type": "wire",
          "width": "[31:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_jesd204_tx",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite transmit engine with JESD204 interface and memory interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
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        {
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          "direction": "in",
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        },
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          "direction": "in",
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        {
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        },
        {
          "direction": "out",
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
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          "width": "[ 6:0]"
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        {
          "direction": "in",
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          "width": "[ 2:0]"
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        {
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        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
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        },
        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
        "package": "axi_ctrlif"
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      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
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        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
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        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
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      {
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
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      },
      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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    ],
    "top_ports": {
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          "direction": "in",
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adc_data",
          "type": "wire",
          "width": "[BITS_PER_SAMPLE-1:0]"
        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": "[15:0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
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          "width": "[ 3:0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        {
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
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        },
        {
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        },
        {
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        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        }
      ]
    }
  },
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      {
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      {
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      {
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    ]
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      {
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    ]
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        },
        {
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        },
        {
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        {
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        },
        {
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        },
        {
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        },
        {
          "direction": "in",
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        },
        {
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        },
        {
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      ]
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    ],
    "top_ports": {
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          "width": ""
        },
        {
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          "name": "s_axi_aresetn",
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        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
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        },
        {
          "direction": "in",
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          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
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        {
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        },
        {
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
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        },
        {
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        {
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        },
        {
          "direction": "out",
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        {
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        },
        {
          "direction": "in",
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        {
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ext_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ext_sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_6",
          "type": "wire",
          "width": ""
        },
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          "direction": "out",
          "name": "pwm_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_9",
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          "width": ""
        },
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          "direction": "out",
          "name": "pwm_10",
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          "width": ""
        },
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          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "pwm_12",
          "type": "wire",
          "width": ""
        },
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          "direction": "out",
          "name": "pwm_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_14",
          "type": "wire",
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        },
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          "direction": "out",
          "name": "pwm_15",
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          "width": ""
        },
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          "direction": "in",
          "name": "period",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
  },
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      "3dc381cf791c",
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      "wr"
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "m_axi_bresp",
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        {
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        },
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        {
          "direction": "out",
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        {
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        {
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        },
        {
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        {
          "direction": "out",
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          "width": ""
        },
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        {
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        },
        {
          "direction": "in",
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        },
        {
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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        {
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        },
        {
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        {
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        },
        {
          "direction": "in",
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        },
        {
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        },
        {
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        {
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
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          "width": "[ 1:0]"
        },
        {
          "direction": "out",
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          "width": "[63:0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_rd_axi_rready",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
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      "HEAD",
      "1336749ccfa9",
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        },
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        },
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        },
        {
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        },
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        },
        {
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        {
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        {
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        {
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        },
        {
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        },
        {
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        {
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        },
        {
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        },
        {
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        {
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        },
        {
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        },
        {
          "direction": "in",
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        {
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        {
          "direction": "out",
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        },
        {
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      ]
    }
  },
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      "HEAD",
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      "spdif"
    ],
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    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
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      {
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        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "provides_packages": [
      "rx_package"
    ],
    "top_ports": {
      "axi_spdif_rx": [
        {
          "direction": "out",
          "name": "rx_int_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spdif_rx_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spdif_rx_i_dbg",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "std_logic_vector",
          "width": "C_S_AXI_ADDR_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "std_logic_vector",
          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "std_logic_vector",
          "width": "(C_S_AXI_DATA_WIDTH/8)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "std_logic_vector",
          "width": "C_S_AXI_ADDR_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "std_logic_vector",
          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "m_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "dma_req_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rstn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_davalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_datype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_daready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_drvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_drtype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_drlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_drready",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_spdif_tx",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite transmit engine with AXI4-Stream interface and memory interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "spdif",
      "transmit",
      "transmitter",
      "tx"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "provides_packages": [
      "tx_package"
    ],
    "top_ports": {
      "axi_spdif_tx": [
        {
          "direction": "in",
          "name": "spdif_data_clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spdif_tx_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "std_logic_vector",
          "width": "S_AXI_ADDRESS_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "std_logic_vector",
          "width": "S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "std_logic_vector",
          "width": "(S_AXI_DATA_WIDTH/8)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "std_logic_vector",
          "width": "S_AXI_ADDRESS_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "std_logic_vector",
          "width": "S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_rstn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_davalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_datype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_daready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_drvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dma_req_drtype",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "dma_req_drlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dma_req_drready",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_spi_engine",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite with SPI interface and ready/valid handshake",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "engine",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_spi_engine": [
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "up_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_wreq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_waddr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "in",
          "name": "up_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "up_wack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rreq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_raddr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "out",
          "name": "up_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "up_rack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_resetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cmd_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmd_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmd_data",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "sdo_data_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdo_data_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdo_data",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "sdi_data_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdi_data_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdi_data",
          "type": "wire",
          "width": "[(NUM_OF_SDI * DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "sync_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "offload0_cmd_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "offload0_cmd_wr_data",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "offload0_sdo_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "offload0_sdo_wr_data",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        },
        {
          "direction": "out",
          "name": "offload0_mem_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "offload0_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "offload0_enabled",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "offload_sync_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "offload_sync_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "offload_sync_data",
          "type": "wire",
          "width": "[7:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_streaming_dma_rx_fifo",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Stream FIFO buffer with configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "access",
      "amba",
      "axi",
      "buffer",
      "bus",
      "direct",
      "fifo",
      "memory",
      "queue",
      "receive",
      "receiver",
      "streaming"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_streaming_dma_rx_fifo": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "Boolean",
          "width": ""
        },
        {
          "direction": "in",
          "name": "period_len",
          "type": "integer",
          "width": "0 to 65535"
        },
        {
          "direction": "in",
          "name": "m_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tkeep",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "in_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "in_ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_data",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_streaming_dma_tx_fifo",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Stream FIFO buffer with configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
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    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "direct",
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      "memory",
      "queue",
      "streaming",
      "transmit",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_streaming_dma_tx_fifo": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "Boolean",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tdata",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "out_ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_data",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_sysid",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite with memory interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "amba",
      "axi",
      "bus",
      "sysid"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "axi_sysid": [
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sys_rom_data",
          "type": "wire",
          "width": "[ROM_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "pr_rom_data",
          "type": "wire",
          "width": "[ROM_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rom_addr",
          "type": "wire",
          "width": "[ROM_ADDR_BITS-1:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_tdd",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license_class": "permissive",
    "language": "systemverilog",
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    "tags": [
      "amba",
      "axi",
      "bus",
      "tdd"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "provides_packages": [
      "axi_tdd_pkg"
    ],
    "top_ports": {
      "axi_tdd": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sync_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "channels",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tdd_channel",
          "type": "wire",
          "width": "[CHANNEL_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[ 9:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[ 9:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "axi_tdd_channel",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates output based on TDD channel data.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "systemverilog",
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    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "axi",
      "bus",
      "channel",
      "tdd"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "provides_packages": [
      "axi_tdd_pkg"
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "axi_tdd_counter",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Counts TDD frames.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "counter",
      "tdd"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "cordic_demod": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_data",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_data",
          "type": "wire",
          "width": "[63:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "corundum_core",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. The original file can be refereed",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "core",
      "corundum"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "corundum_core": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_awid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awaddr",
          "type": "wire",
          "width": "[AXI_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awlen",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awsize",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awburst",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awlock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_awcache",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wdata",
          "type": "wire",
          "width": "[AXI_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_wstrb",
          "type": "wire",
          "width": "[AXI_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_wlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_bid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_arid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_araddr",
          "type": "wire",
          "width": "[AXI_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arlen",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arsize",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arburst",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arlock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_arcache",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_rid",
          "type": "wire",
          "width": "[AXI_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_rdata",
          "type": "wire",
          "width": "[AXI_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_rlast",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_awaddr",
          "type": "wire",
          "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_wdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_wstrb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_araddr",
          "type": "wire",
          "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_rdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_ctrl_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_ctrl_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_csr_awaddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_csr_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_csr_wdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_wstrb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_csr_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_csr_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_csr_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_csr_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_csr_araddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_csr_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_csr_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_csr_rdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_csr_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_csr_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_csr_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_strb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_td_sd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sync_locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sync_ts_rel",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "out",
          "name": "ptp_sync_ts_rel_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sync_ts_tod",
          "type": "wire",
          "width": "[96:0]"
        },
        {
          "direction": "out",
          "name": "ptp_sync_ts_tod_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sync_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sync_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_perout_locked",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ptp_perout_error",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ptp_perout_pulse",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tx_cpl_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tx_cpl_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_tx_cpl_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_tx_cpl_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_fc_quanta_clk_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_lfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_pfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_fc_quanta_clk_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_clk",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_rst",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awaddr",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awlen",
          "type": "wire",
          "width": "[DDR_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awsize",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awburst",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awlock",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awcache",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awprot",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awqos",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awuser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_awready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wdata",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wstrb",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wlast",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wuser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_WUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_wready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bresp",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_buser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_BUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_bready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_araddr",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arlen",
          "type": "wire",
          "width": "[DDR_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arsize",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arburst",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arlock",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arcache",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arprot",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arqos",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_aruser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_arready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rdata",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rresp",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rlast",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_ruser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_RUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_rready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_status",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_clk",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_rst",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awaddr",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awlen",
          "type": "wire",
          "width": "[HBM_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awsize",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awburst",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awlock",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awcache",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awprot",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awqos",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awuser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_awready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wdata",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wstrb",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wlast",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wuser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_WUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_wready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bresp",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_buser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_BUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_bready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_araddr",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arlen",
          "type": "wire",
          "width": "[HBM_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arsize",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arburst",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arlock",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arcache",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arprot",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arqos",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_aruser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_arready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rdata",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rresp",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rlast",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_ruser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_RUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_rready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_status",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_stat_tdata",
          "type": "wire",
          "width": "[STAT_INC_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_stat_tid",
          "type": "wire",
          "width": "[STAT_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_stat_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axis_stat_tready",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "daq2_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI interface controller.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "daq2",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "daq2_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_dir",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "daq3_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Implements SPI interface.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "daq3",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "dma_fifo",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
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    ],
    "description": "DMA FIFO buffer with configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "access",
      "buffer",
      "direct",
      "dma",
      "fifo",
      "memory",
      "queue"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "dma_fifo": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "in_ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_data",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "out_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "out_ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_data",
          "type": "std_logic_vector",
          "width": "FIFO_DWIDTH-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
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    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Dmac IP core with ready/valid handshake and configurable parameters",
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    "license_class": "permissive",
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      "sg"
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    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
        "library": "work",
        "package": "axi_ctrlif"
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      {
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
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    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "buffer",
      "elastic"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
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      {
        "library": "work",
        "package": "axi_ctrlif"
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "ethernet_adrv9009zu11eg",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4-Lite with AXI4-Stream interface and ready/valid handshake",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "adrv9009zu11eg",
      "ethernet"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
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      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ethernet_adrv9009zu11eg": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_led",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_tx_p",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_tx_n",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_p",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_n",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_resetl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_modprsl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_intl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_lpmode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_gtpowergood",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_strb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awaddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wstrb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_araddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_td_sd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod",
          "type": "wire",
          "width": "[96:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_perout_locked",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_error",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_pulse",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_ptp_ts_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_fc_quanta_clk_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_fc_quanta_clk_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "i2c_scl_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_sda_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "frequency",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ethernet_k26",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. The original file can be refereed",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ethernet",
      "k26"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ethernet_k26": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "led",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "sfp_led",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "sfp_rx_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_rx_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sfp_tx_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sfp_tx_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_mgt_refclk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_mgt_refclk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sfp_tx_disable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_tx_fault",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_rx_los",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_mod_abs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_strb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awaddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wstrb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_araddr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_csr_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_csr_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_csr_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_td_sd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod",
          "type": "wire",
          "width": "[96:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_perout_locked",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_error",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_pulse",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_ptp_ts_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_fc_quanta_clk_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_fc_quanta_clk_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "scl_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scl_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scl_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sda_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sda_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sda_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "frequency",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ethernet_vcu118",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. The original file can be refereed",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ethernet",
      "vcu118"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ethernet_vcu118": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_125mhz",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_125mhz",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_drp_clk",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_drp_rst",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_strb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_tx_p",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_tx_n",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_p",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_n",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_modsell",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_resetl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_modprsl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_intl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_lpmode",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_gtpowergood",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_bufg",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_rst",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_ptp_ts_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "i2c_scl_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_sda_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fpga_boot",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qspi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qspi_0_dq_i",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_dq_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_dq_oe",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_cs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qspi_1_dq_i",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_dq_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_dq_oe",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_cs",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "ethernet_xcvu11p",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. The original file can be refereed",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ethernet",
      "xcvu11p"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "ethernet_xcvu11p": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_125mhz",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_125mhz",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_drp_clk",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_drp_rst",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_strb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_wr_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_addr",
          "type": "wire",
          "width": "[AXIL_CSR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_reg_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_data",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_wait",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_reg_rd_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_tx_p",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_tx_n",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_p",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_n",
          "type": "wire",
          "width": "[QSFP_CNT*4-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_modsell",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_resetl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_modprsl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_intl",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_lpmode",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_gtpowergood",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_bufg",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_rst",
          "type": "wire",
          "width": "[QSFP_CNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_tx_ptp_ts_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_tx_ptp_ts_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_tx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_tx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_ptp_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_ptp_ts_step",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "axis_eth_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "axis_eth_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_enable",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_status",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_en",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_lfc_req",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_lfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_en",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "out",
          "name": "eth_rx_pfc_req",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "eth_rx_pfc_ack",
          "type": "wire",
          "width": "[PORT_COUNT*8-1:0]"
        },
        {
          "direction": "in",
          "name": "i2c_scl_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_sda_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_t",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fpga_boot",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qspi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qspi_0_dq_i",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_dq_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_dq_oe",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_0_cs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qspi_1_dq_i",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_dq_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_dq_oe",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi_1_cs",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "fifo_synchronizer",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
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    "description": "FIFO buffer with configurable parameters",
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    "license_class": "permissive",
    "language": "vhdl-2008",
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    "tags": [
      "buffer",
      "fifo",
      "queue",
      "synchronizer"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
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      {
        "library": "work",
        "package": "fifo_synchronizer"
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      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
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      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
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      }
    ],
    "top_ports": {
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          "direction": "in",
          "name": "in_clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_data",
          "type": "std_logic_vector",
          "width": "WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "in_tick",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "out_clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "out_resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_data",
          "type": "std_logic_vector",
          "width": "WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "out_tick",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "fmcomms11_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
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      "fmcomms11",
      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
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      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "fmcomms11_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_ad9625",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_ad9162",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_ad9508",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_adl5240",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_adf4355",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_hmc1119",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_dir",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
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    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "interface",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
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      {
        "library": "work",
        "package": "dma_fifo"
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      {
        "library": "work",
        "package": "fifo_synchronizer"
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      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
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      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "fmcomms8_spi": [
        {
          "direction": "in",
          "name": "spi_csn",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_miso_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "gpio_slave",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI slave",
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "gpio",
      "input",
      "output",
      "purpose",
      "slave"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      {
        "library": "work",
        "package": "axi_ctrlif"
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      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
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      {
        "library": "work",
        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "gpio_slave": [
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "leds",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "dipsw",
          "type": "wire",
          "width": "[7:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "hsci_master_axi_slave",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
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    "language": "systemverilog",
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      "axi",
      "bus",
      "hsci",
      "master",
      "slave"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
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      {
        "library": "work",
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      {
        "library": "work",
        "package": "dma_fifo"
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      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
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      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "hsci_master_logic",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license": "ADIBSD OR GPL-2.0-only",
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        "library": "work",
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        {
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          "name": "ack",
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        },
        {
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
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        "package": "axi_streaming_dma_rx_fifo"
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      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
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        "library": "work",
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        "library": "work",
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        "package": "i2s_controller"
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        {
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        },
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          "direction": "in",
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          "type": "std_logic_vector",
          "width": "C_SLOT_WIDTH-1 downto 0"
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      ]
    }
  },
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    "description": "SPI controller with ready/valid handshake",
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          "direction": "out",
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          "width": "[6:0]"
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          "name": "rmap_dev_char_data",
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        "library": "work",
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    ]
  },
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    "description": "AXI4-Lite controller with SPI interface and ready/valid handshake",
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    ],
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          "name": "clk",
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        },
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          "direction": "out",
          "name": "reset_n",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
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        },
        {
          "direction": "in",
          "name": "s_axi_rready",
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        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "offload_trigger",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "cmdp_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmdp_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmdp",
          "type": "wire",
          "width": "[30:0]"
        },
        {
          "direction": "in",
          "name": "cmdp_error",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "cmdp_nop",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cmdp_daa_trigger",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdo_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "sdi_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdi_valid",
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          "width": ""
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          "type": "wire",
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          "width": "[  7 : 0]"
        },
        {
          "direction": "in",
          "name": "tx_data",
          "type": "wire",
          "width": "[ 63 : 0]"
        },
        {
          "direction": "in",
          "name": "tx_header",
          "type": "wire",
          "width": "[  1 : 0]"
        },
        {
          "direction": "in",
          "name": "tx_charisk",
          "type": "wire",
          "width": "[  3 : 0]"
        },
        {
          "direction": "in",
          "name": "usr_clk",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "m2k_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Implements SPI interface.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "interface",
      "m2k",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "m2k_spi": [
        {
          "direction": "in",
          "name": "ad9963_csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adf4360_cs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi_sdio",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "mqnic_app_block",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "AXI4 with AXI4-Stream interface and ready/valid handshake",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "app",
      "block",
      "mqnic"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "mqnic_app_block": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_awaddr",
          "type": "wire",
          "width": "[AXIL_APP_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_wdata",
          "type": "wire",
          "width": "[AXIL_APP_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_wstrb",
          "type": "wire",
          "width": "[AXIL_APP_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_araddr",
          "type": "wire",
          "width": "[AXIL_APP_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_rdata",
          "type": "wire",
          "width": "[AXIL_APP_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axil_app_ctrl_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axil_app_ctrl_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_awaddr",
          "type": "wire",
          "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_awprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_wdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_wstrb",
          "type": "wire",
          "width": "[AXIL_CTRL_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_araddr",
          "type": "wire",
          "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_arprot",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_rdata",
          "type": "wire",
          "width": "[AXIL_CTRL_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "m_axil_ctrl_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axil_ctrl_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_dma_addr",
          "type": "wire",
          "width": "[DMA_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_ram_sel",
          "type": "wire",
          "width": "[RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_ram_addr",
          "type": "wire",
          "width": "[RAM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_len",
          "type": "wire",
          "width": "[DMA_LEN_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_read_desc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_ctrl_dma_read_desc_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_read_desc_status_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_read_desc_status_error",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_read_desc_status_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_dma_addr",
          "type": "wire",
          "width": "[DMA_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_ram_sel",
          "type": "wire",
          "width": "[RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_ram_addr",
          "type": "wire",
          "width": "[RAM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_imm",
          "type": "wire",
          "width": "[DMA_IMM_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_imm_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_len",
          "type": "wire",
          "width": "[DMA_LEN_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_ctrl_dma_write_desc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_ctrl_dma_write_desc_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_write_desc_status_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_write_desc_status_error",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_ctrl_dma_write_desc_status_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_dma_addr",
          "type": "wire",
          "width": "[DMA_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_ram_sel",
          "type": "wire",
          "width": "[RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_ram_addr",
          "type": "wire",
          "width": "[RAM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_len",
          "type": "wire",
          "width": "[DMA_LEN_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_read_desc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_data_dma_read_desc_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_read_desc_status_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_read_desc_status_error",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_read_desc_status_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_dma_addr",
          "type": "wire",
          "width": "[DMA_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_ram_sel",
          "type": "wire",
          "width": "[RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_ram_addr",
          "type": "wire",
          "width": "[RAM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_imm",
          "type": "wire",
          "width": "[DMA_IMM_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_imm_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_len",
          "type": "wire",
          "width": "[DMA_LEN_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_dma_write_desc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_data_dma_write_desc_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_write_desc_status_tag",
          "type": "wire",
          "width": "[DMA_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_write_desc_status_error",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_data_dma_write_desc_status_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_wr_cmd_sel",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_wr_cmd_be",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_wr_cmd_addr",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_wr_cmd_data",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_wr_cmd_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_dma_ram_wr_cmd_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_dma_ram_wr_done",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_rd_cmd_sel",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_rd_cmd_addr",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_rd_cmd_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_dma_ram_rd_cmd_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_dma_ram_rd_resp_data",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "ctrl_dma_ram_rd_resp_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ctrl_dma_ram_rd_resp_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_wr_cmd_sel",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_wr_cmd_be",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_wr_cmd_addr",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_wr_cmd_data",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_wr_cmd_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "data_dma_ram_wr_cmd_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "data_dma_ram_wr_done",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_rd_cmd_sel",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_rd_cmd_addr",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_rd_cmd_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "data_dma_ram_rd_cmd_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "data_dma_ram_rd_resp_data",
          "type": "wire",
          "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "data_dma_ram_rd_resp_valid",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "data_dma_ram_rd_resp_ready",
          "type": "wire",
          "width": "[RAM_SEG_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sample_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_td_sd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_rel_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod",
          "type": "wire",
          "width": "[PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_sync_ts_tod_step",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_sync_pps_str",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ptp_perout_locked",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_error",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "ptp_perout_pulse",
          "type": "wire",
          "width": "[PTP_PEROUT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "direct_tx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "direct_tx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_direct_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_direct_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_cpl_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_cpl_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_tx_cpl_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_direct_tx_cpl_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_cpl_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_cpl_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_tx_cpl_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_direct_tx_cpl_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "direct_rx_clk",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "direct_rx_rst",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_direct_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_direct_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_direct_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_direct_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_sync_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_sync_tx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_cpl_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_cpl_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_tx_cpl_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_sync_tx_cpl_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_cpl_ts",
          "type": "wire",
          "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_cpl_tag",
          "type": "wire",
          "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_tx_cpl_valid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_sync_tx_cpl_ready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_sync_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sync_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_rx_tdata",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_rx_tkeep",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_rx_tvalid",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_sync_rx_tready",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_rx_tlast",
          "type": "wire",
          "width": "[PORT_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_sync_rx_tuser",
          "type": "wire",
          "width": "[PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tdata",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tkeep",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tvalid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_if_tx_tready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tlast",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tid",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tdest",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_tuser",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tdata",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tkeep",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tvalid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_if_tx_tready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tlast",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tid",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tdest",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_tuser",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_cpl_ts",
          "type": "wire",
          "width": "[IF_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_cpl_tag",
          "type": "wire",
          "width": "[IF_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_tx_cpl_valid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_if_tx_cpl_ready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_cpl_ts",
          "type": "wire",
          "width": "[IF_COUNT*PTP_TS_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_cpl_tag",
          "type": "wire",
          "width": "[IF_COUNT*TX_TAG_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_tx_cpl_valid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_if_tx_cpl_ready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tdata",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tkeep",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tvalid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "s_axis_if_rx_tready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tlast",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tid",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tdest",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "s_axis_if_rx_tuser",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tdata",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tkeep",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tvalid",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axis_if_rx_tready",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tlast",
          "type": "wire",
          "width": "[IF_COUNT-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tid",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tdest",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_if_rx_tuser",
          "type": "wire",
          "width": "[IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_clk",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_rst",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awaddr",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awlen",
          "type": "wire",
          "width": "[DDR_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awsize",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awburst",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awlock",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awcache",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awprot",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awqos",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awuser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_awvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_awready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wdata",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wstrb",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wlast",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wuser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_WUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_wvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_wready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bresp",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_buser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_BUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_bvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_bready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_araddr",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arlen",
          "type": "wire",
          "width": "[DDR_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arsize",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arburst",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arlock",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arcache",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arprot",
          "type": "wire",
          "width": "[DDR_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arqos",
          "type": "wire",
          "width": "[DDR_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_aruser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_arvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_arready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rid",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rdata",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rresp",
          "type": "wire",
          "width": "[DDR_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rlast",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_ruser",
          "type": "wire",
          "width": "[DDR_CH*AXI_DDR_RUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_ddr_rvalid",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_ddr_rready",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "ddr_status",
          "type": "wire",
          "width": "[DDR_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_clk",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_rst",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awaddr",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awlen",
          "type": "wire",
          "width": "[HBM_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awsize",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awburst",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awlock",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awcache",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awprot",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awqos",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awuser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_awvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_awready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wdata",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wstrb",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_STRB_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wlast",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wuser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_WUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_wvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_wready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bresp",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_buser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_BUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_bvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_bready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_araddr",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arlen",
          "type": "wire",
          "width": "[HBM_CH*8-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arsize",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arburst",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arlock",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arcache",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arprot",
          "type": "wire",
          "width": "[HBM_CH*3-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arqos",
          "type": "wire",
          "width": "[HBM_CH*4-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_aruser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_arvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_arready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rid",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rdata",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rresp",
          "type": "wire",
          "width": "[HBM_CH*2-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rlast",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_ruser",
          "type": "wire",
          "width": "[HBM_CH*AXI_HBM_RUSER_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "m_axi_hbm_rvalid",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_hbm_rready",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "in",
          "name": "hbm_status",
          "type": "wire",
          "width": "[HBM_CH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_stat_tdata",
          "type": "wire",
          "width": "[STAT_INC_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_stat_tid",
          "type": "wire",
          "width": "[STAT_ID_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_stat_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axis_stat_tready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_in",
          "type": "wire",
          "width": "[APP_GPIO_IN_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "gpio_out",
          "type": "wire",
          "width": "[APP_GPIO_OUT_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "jtag_tdi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_tdo",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tms",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tck",
          "type": "wire",
          "width": ""
        }
      ]
    }
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
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          "direction": "out",
          "name": "DBG",
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        {
          "direction": "inout",
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        {
          "direction": "inout",
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        {
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          "name": "mxfe1_gpio6",
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          "width": ""
        },
        {
          "direction": "inout",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
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          "direction": "inout",
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        {
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          "direction": "inout",
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        },
        {
          "direction": "inout",
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          "width": ""
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        {
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        },
        {
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        },
        {
          "direction": "inout",
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          "width": ""
        },
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          "direction": "inout",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mxfe2_gpio6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
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          "type": "wire",
          "width": ""
        },
        {
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          "name": "mxfe2_gpio8",
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          "width": ""
        },
        {
          "direction": "inout",
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          "width": ""
        },
        {
          "direction": "inout",
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        },
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        },
        {
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          "width": "[127:64]"
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          "direction": "out",
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          "name": "values",
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        }
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    "description": "WISHBONE SPDIF IP Core                                       ----",
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      },
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        "library": "work",
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      {
        "library": "work",
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        "library": "work",
        "package": "pl330_dma_fifo"
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      "rx_package"
    ],
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          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "ch_data",
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          "direction": "in",
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        {
          "direction": "in",
          "name": "ud_b_en",
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          "width": ""
        },
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          "direction": "in",
          "name": "cs_a_en",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
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          "direction": "out",
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          "direction": "out",
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        },
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          "direction": "in",
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        },
        {
          "direction": "in",
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          "width": "[15:0]"
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        {
          "direction": "in",
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        },
        {
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          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
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        {
          "direction": "in",
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        {
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          "direction": "out",
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        },
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          "direction": "out",
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          "direction": "in",
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          "direction": "out",
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        {
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        {
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        {
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        {
          "direction": "in",
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        {
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        },
        {
          "direction": "in",
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          "width": "[7:0]"
        },
        {
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "s0_sdo_valid",
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        },
        {
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
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        },
        {
          "direction": "out",
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    ],
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        },
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        },
        {
          "direction": "in",
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        {
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        },
        {
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_enabled",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
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        },
        {
          "direction": "in",
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        },
        {
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_resetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trigger",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmd_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cmd_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cmd",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "sdo_data_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_data_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdo_data",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        },
        {
          "direction": "in",
          "name": "s_axis_sdo_data",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        },
        {
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        {
          "direction": "in",
          "name": "usb1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "usb1_stp",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "usb1_dir",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "usb1_nxt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "usb1_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "spim1_ss0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spim1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spim1_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spim1_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart0_tx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_bd_o",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "gpio_bd_i",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_blank_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_sync_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_red",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_grn",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_blu",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "lvds_cmos_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cnv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cs_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo",
          "type": "wire",
          "width": "[ 7:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "system_top_corundum",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI with I2C interface and configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "corundum",
      "system"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "system_top_corundum": [
        {
          "direction": "in",
          "name": "sys_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sys_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sys_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_sin",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart_sout",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr4_act_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr4_addr",
          "type": "wire",
          "width": "[16:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_ba",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_bg",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_ck_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr4_ck_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr4_cke",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_cs_n",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "inout",
          "name": "ddr4_dm_n",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "inout",
          "name": "ddr4_dq",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "inout",
          "name": "ddr4_dqs_p",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "inout",
          "name": "ddr4_dqs_n",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_odt",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "ddr4_reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mdio_mdc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mdio_mdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_clk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "phy_rst_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_rx_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_rx_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "phy_tx_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "phy_tx_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "gpio_bd",
          "type": "wire",
          "width": "[16:0]"
        },
        {
          "direction": "out",
          "name": "iic_rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "iic_scl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "iic_sda",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vadj_1v8_pgood",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "agc0",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "agc1",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "agc2",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "agc3",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "clkin8_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clkin8_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clkin6_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clkin6_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fpga_refclk_in_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fpga_refclk_in_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fpga_refclk_in_replica_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fpga_refclk_in_replica_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_data_n",
          "type": "wire",
          "width": "[RX_JESD_L*RX_NUM_LINKS-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_data_p",
          "type": "wire",
          "width": "[RX_JESD_L*RX_NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_data_n",
          "type": "wire",
          "width": "[TX_JESD_L*TX_NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "tx_data_p",
          "type": "wire",
          "width": "[TX_JESD_L*TX_NUM_LINKS-1:0]"
        },
        {
          "direction": "in",
          "name": "fpga_syncin_n",
          "type": "wire",
          "width": "[TX_NUM_LINKS-1:0]"
        },
        {
          "direction": "in",
          "name": "fpga_syncin_p",
          "type": "wire",
          "width": "[TX_NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "fpga_syncout_n",
          "type": "wire",
          "width": "[RX_NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "fpga_syncout_p",
          "type": "wire",
          "width": "[RX_NUM_LINKS-1:0]"
        },
        {
          "direction": "inout",
          "name": "gpio",
          "type": "wire",
          "width": "[10:0]"
        },
        {
          "direction": "inout",
          "name": "hmc_gpio1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hmc_sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irqb",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rstb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rxen",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "spi0_csb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi0_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi0_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi0_sclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi1_csb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi1_sclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "spi1_sdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sysref2_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sysref2_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "txen",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_mgt_refclk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_tx_p",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qsfp_tx_n",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_p",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "qsfp_rx_n",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "inout",
          "name": "qspi1_dq",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "qspi1_cs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_modsell",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_resetl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_modprsl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qsfp_intl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qsfp_lpmode",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "system_top_lvds",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI with MDIO interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "differential",
      "low",
      "lvds",
      "signaling",
      "system",
      "voltage"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "system_top_lvds": [
        {
          "direction": "in",
          "name": "sys_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_a",
          "type": "wire",
          "width": "[14:0]"
        },
        {
          "direction": "out",
          "name": "ddr3_ba",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "out",
          "name": "ddr3_reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_ck_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_ck_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_cke",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_cs_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_ras_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_cas_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ddr3_we_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ddr3_dq",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "inout",
          "name": "ddr3_dqs_p",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "inout",
          "name": "ddr3_dqs_n",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "ddr3_dm",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "ddr3_odt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ddr3_rzq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eth1_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eth1_tx_ctl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eth1_tx_d",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "eth1_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eth1_rx_ctl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eth1_rx_d",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "eth1_mdc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "eth1_mdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qspi_ss0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qspi_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "qspi_io",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "sdio_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "sdio_cmd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "sdio_d",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "usb1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "usb1_stp",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "usb1_dir",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "usb1_nxt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "usb1_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "spim1_ss0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spim1_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spim1_mosi",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spim1_miso",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart0_tx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_bd_o",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "gpio_bd_i",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_blank_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_sync_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "vga_red",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_grn",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "vga_blu",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "lvds_cmos_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cnv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cs_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdi_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdi_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scki_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scko_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdo_n",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "trigger_generator",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
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    "tags": [
      "generator",
      "trigger"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "trigger_generator": [
        {
          "direction": "in",
          "name": "sysref",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "device_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trigger",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "up_ad5766_sequencer",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Generates sequence data.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "ad5766",
      "sequencer"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_adc_channel",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Controlles ADC channel.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
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      "analog",
      "channel",
      "converter",
      "digital"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_adc_common",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Analog IP core with memory interface and interrupt support",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
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      "analog",
      "common",
      "converter",
      "digital"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_clkgen",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
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    ],
    "description": "Generator with memory interface",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
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    "tags": [
      "clkgen"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
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        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
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      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
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        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_dac_channel",
    "latest": "3dc381cf791c",
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      "1336749ccfa9",
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    ],
    "description": "Generates DAC outputs.",
    "license": "ADIBSD OR GPL-2.0-only",
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    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "dac",
      "digital"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
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        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_dac_common",
    "latest": "3dc381cf791c",
    "versions": [
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      "ca0618ef7b4f",
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      "0.0.0"
    ],
    "description": "Digital IP core with memory interface and interrupt support",
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
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      "common",
      "converter",
      "dac",
      "digital"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
    "external_uses": [
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        "package": "axi_ctrlif"
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      {
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      },
      {
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      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
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        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_delay_cntrl",
    "latest": "3dc381cf791c",
    "versions": [
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
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      "0.0.0"
    ],
    "description": "Configurable delay controller with register-based processor interface for multiple delay channels and DRP readback.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "cntrl",
      "delay"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "verdict",
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      },
      {
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        "package": "axi_streaming_dma_rx_fifo"
      },
      {
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        "package": "axi_streaming_dma_tx_fifo"
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      {
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      {
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      {
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        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
  },
  {
    "namespace": "analog-devices",
    "name": "up_hdmi_rx",
    "latest": "3dc381cf791c",
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      "HEAD",
      "1336749ccfa9",
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    ],
    "description": "Receive engine",
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    "tags": [
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      "receive",
      "receiver",
      "rx"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
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      {
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        "package": "axi_streaming_dma_rx_fifo"
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      {
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      {
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      {
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      {
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      {
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      {
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        "package": "i2s_tx"
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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    ]
  },
  {
    "namespace": "analog-devices",
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    ],
    "description": "Transmit engine",
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    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
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      "transmit",
      "transmitter",
      "tx"
    ],
    "role": "component",
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        {
          "direction": "in",
          "name": "up_tx_wdata_0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_1_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_1_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_1",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_1_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_1_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_1",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_1",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_1",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_1",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_1",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_1",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_1",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_1",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_1",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_1",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_1",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_1",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_2_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_2_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_2",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_2_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_2_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_2",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_2",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_2",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_2",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_2",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_2",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_2",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_2",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_2",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_3_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_3_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_3",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_3_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_3_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_3",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_3",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_3",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_3",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_3",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_3",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_3",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_3",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_3",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_4_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_4_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_4",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_4_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_4_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_4",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_4",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_4",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_4",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_4",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_4",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_4",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_5_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_5_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_5",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_5_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_5_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_5",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_5",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_5",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_5",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_5",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_5",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_5",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_5",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_5",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_6_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_6_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_6",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_6_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_6_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_6",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_6",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_6",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_6",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_6",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_6",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_6",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_6",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_6",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_7_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_7_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_7",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_7_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_7_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_7",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_7",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_7",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_7",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_7",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_7",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_7",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_7",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_7",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_7",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_8_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_8_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_8",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_8_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_8_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_8",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_8",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_8",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_8",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_8",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_8",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_8",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_8",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_8",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_9_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_9_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_9",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_9_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_9_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_9",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_9",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_9",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_9",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_9",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_9",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_9",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_9",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_9",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_9",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_9",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_10_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_10_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_10",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_10_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_10_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_10",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_10",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_10",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_10",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_10",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_10",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_10",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_10",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_10",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_10",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_10",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_11_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_11_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_11",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_11_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_11_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_11",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_11",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_11",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_11",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_11",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_11",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_11",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_11",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_11",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_11",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_11",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_12_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_12_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_12",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_12_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_12_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_12",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_12",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_12",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_12",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_12",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_12",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_12",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_12",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_12",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_13_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_13_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_13",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_13_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_13_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_13",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_13",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_13",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_13",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_13",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_13",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_13",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_13",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_13",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_13",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_13",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_14_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_14_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_14",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_14_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_14_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_14",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_14",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_14",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_14",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_14",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_14",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_14",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_14",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_14",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_14",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_14",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_15_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_15_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_15",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_15_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_15_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_15",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_15",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_15",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_15",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_15",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_15",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_15",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_15",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_15",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_15",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_15",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_16_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_16_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_16",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_16_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_16_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_16",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_16",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_16",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_16",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_16",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_16",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_16",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_16",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_17_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_17_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_17",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_17_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_17_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_17",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_17",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_17",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_17",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_17",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_17",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_17",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_17",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_17",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_17",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_17",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_18_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_18_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_18",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_18_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_18_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_18",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_18",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_18",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_18",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_18",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_18",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_18",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_18",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_18",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_18",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_18",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_19_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_19_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_19",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_19_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_19_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_19",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_19",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_19",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_19",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_19",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_19",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_19",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_19",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_19",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_19",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_19",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_20_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_20_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_20",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_20_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_20_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_20",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_20",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_20",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_20",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_20",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_20",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_20",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_20",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_20",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_21_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_21_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_21",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_21_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_21_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_21",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_21",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_21",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_21",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_21",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_21",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_21",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_21",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_21",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_21",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_21",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_22_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_22_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_22",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_22_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_22_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_22",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_22",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_22",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_22",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_22",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_22",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_22",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_22",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_22",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_22",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_22",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_23_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_23_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_23",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_23_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_23_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_23",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_23",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_23",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_23",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_23",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_23",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_23",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_23",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_23",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_23",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_23",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_24_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_24_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_24",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_24_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_24_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_24",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_24",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_24",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_24",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_24",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_24",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_24",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_24",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_24",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_25_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_25_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_25",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_25_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_25_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_25",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_25",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_25",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_25",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_25",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_25",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_25",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_25",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_25",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_25",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_25",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_26_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_26_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_26",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_26_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_26_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_26",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_26",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_26",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_26",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_26",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_26",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_26",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_26",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_26",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_26",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_26",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_27_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_27_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_27",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_27_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_27_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_27",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_27",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_27",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_27",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_27",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_27",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_27",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_27",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_27",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_27",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_27",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "qpll_ref_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_qpll_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_28_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_28_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_28",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_28_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_28_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_28",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_28",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_cm_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cm_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_cm_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_28",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_28",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_28",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_28",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_28",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_28",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_28",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_29_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_29_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_29",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_29_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_29_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_29",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_29",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_29",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_29",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_29",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_29",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_29",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_29",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_29",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_29",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_29",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_30_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_30_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_30",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_30_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_30_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_30",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_30",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_30",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_30",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_30",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_rdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_rx_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_pll_locked_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rst_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_user_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_rst_done_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_tx_bufstatus_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_prbsforceerr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_prbssel_30",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_lpm_dfe_n_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_rate_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_sys_clk_sel_30",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_out_clk_sel_30",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_diffctrl_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_postcursor_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_precursor_30",
          "type": "wire",
          "width": "[ 4:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_enb_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_addr_30",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_tx_wr_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_tx_wdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_rdata_30",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_tx_ready_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpll_ref_clk_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_cpll_rst_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_31_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_31_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_out_clk_div2_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_clk_2x_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_charisk_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_disperr_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_notintable_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_data_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_calign_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_header_31",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rx_block_sync_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_31_p",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_31_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_out_clk_div2_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_clk_2x_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_charisk_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_data_31",
          "type": "wire",
          "width": "[DATA_PATH_WIDTH*8-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_header_31",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "up_es_enb_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_addr_31",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_es_wr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_wdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_rdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "up_es_ready_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_es_reset_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_pll_locked_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rst_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_user_ready_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_rst_done_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_prbssel_31",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_prbscntreset_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbserr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_prbslocked_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "up_rx_bufstatus_31",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_bufstatus_rst_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_lpm_dfe_n_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_rate_31",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_sys_clk_sel_31",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_out_clk_sel_31",
          "type": "wire",
          "width": "[ 2:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_enb_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_addr_31",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "in",
          "name": "up_rx_wr_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "up_rx_wdata_31",
          "type": "wire",
          "width": "[15:0]"
        },
        {
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          "name": "clk_out",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "util_cpack2",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Packs channel data.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "cpack2",
      "util"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "util_cpack2": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_9",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_11",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_12",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_13",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_14",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_15",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_17",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_18",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_19",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_20",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_21",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_22",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_23",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_24",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_25",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_26",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_27",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_28",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_29",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_30",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_31",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_33",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_34",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_35",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_36",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_37",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_38",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_39",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_40",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_41",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_42",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_43",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_44",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_45",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_46",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_47",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_48",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_49",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_50",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_51",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_52",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_53",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_54",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_55",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_56",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_57",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_58",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_59",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_60",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_61",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_62",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_63",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifo_wr_overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_0",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_1",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_2",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_3",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_4",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_5",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_6",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_7",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_8",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_9",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_10",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_11",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_12",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_13",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_14",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_15",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_16",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_17",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_18",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_19",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_20",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_21",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_22",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_23",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_24",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_25",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_26",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_27",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_28",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_29",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_30",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_31",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_32",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_33",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_34",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_35",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_36",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_37",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_38",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_39",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_40",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_41",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_42",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_43",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_44",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_45",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_46",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_47",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_48",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_49",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_50",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_51",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_52",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_53",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_54",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_55",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_56",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_57",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_58",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_59",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_60",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_61",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_62",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "in",
          "name": "fifo_wr_data_63",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "packed_fifo_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "packed_fifo_wr_overflow",
          "type": "wire",
          "width": ""
        },
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          "direction": "out",
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
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          "direction": "in",
          "name": "aclk",
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        },
        {
          "direction": "in",
          "name": "s_axis_data_tvalid",
          "type": "wire",
          "width": ""
        },
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          "width": ""
        },
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          "direction": "in",
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          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "channel_0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "channel_1",
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          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "m_axis_data_tvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interpolate",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_read",
          "type": "wire",
          "width": ""
        }
      ]
    }
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      "1336749ccfa9",
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      "interface",
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      "util"
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    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
        "package": "pl330_dma_fifo"
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          "name": "clk_20m",
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          "direction": "in",
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          "width": ""
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          "direction": "in",
          "name": "idelayctrl_clk",
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          "width": ""
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
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          "direction": "in",
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          "width": "[ 3:0]"
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          "direction": "in",
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          "type": "wire",
          "width": "[ 7:0]"
        },
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          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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        {
          "direction": "out",
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          "width": ""
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          "direction": "out",
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          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
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          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "gmii_rx_er",
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          "direction": "out",
          "name": "gmii_rx_clk",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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        {
          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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        {
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        {
          "direction": "in",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "m_axis_data",
          "type": "wire",
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        {
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
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        },
        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
          "direction": "in",
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          "direction": "out",
          "name": "m_axi_wvalid",
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        {
          "direction": "out",
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        {
          "direction": "in",
          "name": "m_axi_bvalid",
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          "width": "[NUM_M-1:0]"
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        {
          "direction": "in",
          "name": "m_axi_bresp",
          "type": "wire",
          "width": "[NUM_M*2-1:0]"
        },
        {
          "direction": "out",
          "name": "m_axi_bready",
          "type": "wire",
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        {
          "direction": "in",
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        {
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        {
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        {
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        {
          "direction": "in",
          "name": "m_axi_rlast",
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          "width": "[NUM_M-1:0]"
        }
      ]
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  },
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      "HEAD",
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      "util"
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    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "ports",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "util_mfifo": [
        {
          "direction": "in",
          "name": "din_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_0",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_1",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_2",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_3",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_4",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_5",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_6",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_data_7",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_0",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_1",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_2",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_3",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_4",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_5",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_6",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "dout_data_7",
          "type": "wire",
          "width": "[15:0]"
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "util_mii_to_rmii",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "MII to RMII converter.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "independent",
      "interface",
      "media",
      "mii",
      "rmii",
      "util"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
        "package": "i2s_clkgen"
      },
      {
        "library": "work",
        "package": "i2s_controller"
      },
      {
        "library": "work",
        "package": "i2s_rx"
      },
      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "util_mii_to_rmii": [
        {
          "direction": "in",
          "name": "mac_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mac_txd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "mac_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_col",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_crs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_rxd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "rmii_txd",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "rmii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_rxd",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "phy_crs_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phy_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ref_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "util_pad",
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "Pads input data samples.",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
    "tags": [
      "pad",
      "util"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
    "desc_source": "preserved",
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      {
        "library": "work",
        "package": "axi_ctrlif"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
      },
      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
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      },
      {
        "library": "work",
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      },
      {
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      {
        "library": "work",
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      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
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        {
          "direction": "in",
          "name": "data_in",
          "type": "wire",
          "width": "[NUM_OF_SAMPLES*IN_BITS_PER_SAMPLE-1:0]"
        },
        {
          "direction": "out",
          "name": "data_out",
          "type": "wire",
          "width": "[NUM_OF_SAMPLES*OUT_BITS_PER_SAMPLE-1:0]"
        }
      ]
    }
  },
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    "latest": "3dc381cf791c",
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
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    "license_class": "permissive",
    "language": "verilog",
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    "tags": [
      "rfifo",
      "util"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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        "library": "work",
        "package": "axi_ctrlif"
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      {
        "library": "work",
        "package": "axi_streaming_dma_rx_fifo"
      },
      {
        "library": "work",
        "package": "axi_streaming_dma_tx_fifo"
      },
      {
        "library": "work",
        "package": "dma_fifo"
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      {
        "library": "work",
        "package": "fifo_synchronizer"
      },
      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
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      {
        "library": "work",
        "package": "i2s_tx"
      },
      {
        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
    "top_ports": {
      "util_rfifo": [
        {
          "direction": "in",
          "name": "din_rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_0",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_1",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_2",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_3",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_4",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_5",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_6",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "din_enable_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "din_valid_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_valid_in_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_data_7",
          "type": "wire",
          "width": "[DIN_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "din_unf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_0",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_1",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_2",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_3",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_4",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_5",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_6",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dout_enable_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dout_valid_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_valid_out_7",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_data_7",
          "type": "wire",
          "width": "[DOUT_DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "dout_unf",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "analog-devices",
    "name": "util_sigma_delta_spi",
    "latest": "3dc381cf791c",
    "versions": [
      "3dc381cf791c",
      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
      "0.0.0"
    ],
    "description": "SPI with configurable parameters",
    "license": "ADIBSD OR GPL-2.0-only",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/analogdevicesinc/hdl.git",
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      "interface",
      "peripheral",
      "serial",
      "sigma",
      "spi",
      "util"
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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        "package": "axi_streaming_dma_rx_fifo"
      },
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      },
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      },
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        "package": "pl330_dma_fifo"
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          "name": "resetn",
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        {
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          "type": "wire",
          "width": ""
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          "direction": "out",
          "name": "data_ready",
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          "width": ""
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      ]
    }
  },
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    "license_class": "permissive",
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    "updated_at": "2026-05-13T08:20:05+00:00",
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          "name": "rstn",
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          "width": ""
        },
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          "name": "sync_mode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sync_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "assign",
          "type": "wire",
          "width": ""
        }
      ]
    }
  },
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    "namespace": "analog-devices",
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      "HEAD",
      "1336749ccfa9",
      "ca0618ef7b4f",
      "7b364c5dfd5e",
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    "license_class": "permissive",
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      "util"
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    "role": "top",
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    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-13T08:20:05+00:00",
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      },
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        "library": "work",
        "package": "fifo_synchronizer"
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        "library": "work",
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        "library": "work",
        "package": "i2s_controller"
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      {
        "library": "work",
        "package": "i2s_rx"
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      {
        "library": "work",
        "package": "i2s_tx"
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        "library": "work",
        "package": "pl330_dma_fifo"
      }
    ],
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          "name": "clk",
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          "width": ""
        },
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          "direction": "in",
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          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_2",
          "type": "wire",
          "width": ""
        },
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          "name": "enable_3",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "enable_4",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_5",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_7",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "enable_8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_9",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "enable_10",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_11",
          "type": "wire",
          "width": ""
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          "name": "enable_12",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_13",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "enable_14",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_15",
          "type": "wire",
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        {
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          "name": "enable_16",
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          "width": ""
        },
        {
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          "name": "enable_17",
          "type": "wire",
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          "direction": "in",
          "name": "enable_18",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_19",
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          "width": ""
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        {
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          "width": ""
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          "name": "enable_21",
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          "width": ""
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_23",
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          "width": ""
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          "type": "wire",
          "width": ""
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          "direction": "in",
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          "name": "enable_35",
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          "name": "enable_38",
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          "direction": "in",
          "name": "enable_39",
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          "width": ""
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          "name": "enable_40",
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        {
          "direction": "in",
          "name": "enable_41",
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          "width": ""
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        {
          "direction": "in",
          "name": "enable_42",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "enable_43",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_44",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_45",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_46",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_47",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_48",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_49",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_50",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_51",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_52",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_53",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_54",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_55",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_56",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_57",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_58",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_59",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_60",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_61",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_62",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_63",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fifo_rd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifo_rd_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifo_rd_underflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_0",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_1",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_2",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_3",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_4",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_5",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
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          "name": "fifo_rd_data_6",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_7",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_8",
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          "name": "fifo_rd_data_9",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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          "name": "fifo_rd_data_12",
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          "name": "fifo_rd_data_13",
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          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
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          "name": "fifo_rd_data_14",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_15",
          "type": "wire",
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          "direction": "out",
          "name": "fifo_rd_data_16",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_17",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_18",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_19",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_20",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_21",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_22",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_23",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_24",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_25",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_26",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_27",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_28",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_29",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
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          "direction": "out",
          "name": "fifo_rd_data_30",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_31",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
          "name": "fifo_rd_data_32",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
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        {
          "direction": "out",
          "name": "fifo_rd_data_33",
          "type": "wire",
          "width": "[SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0]"
        },
        {
          "direction": "out",
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          "direction": "in",
          "name": "hb_din",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "z_low",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "z_hi",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "hb_dout",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "low_factor",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "high_factor",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "fog64",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "de3d_read_addr_in": [
        {
          "direction": "in",
          "name": "de_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bpt",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ul_tag_adr_rd",
          "type": "wire",
          "width": "[14:0]"
        },
        {
          "direction": "in",
          "name": "ll_tag_adr_rd",
          "type": "wire",
          "width": "[14:0]"
        },
        {
          "direction": "in",
          "name": "ur_tag_adr_rd",
          "type": "wire",
          "width": "[14:0]"
        },
        {
          "direction": "in",
          "name": "lr_tag_adr_rd",
          "type": "wire",
          "width": "[14:0]"
        },
        {
          "direction": "out",
          "name": "ee_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "eo_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "oe_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "oo_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        }
      ],
      "de3d_tfog": [
        {
          "direction": "in",
          "name": "de_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hb_csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hb_tfog_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hb_wstrb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hb_addr",
          "type": "wire",
          "width": "[6:2]"
        },
        {
          "direction": "in",
          "name": "hb_ben",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "hb_din",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "zvalue",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "in",
          "name": "pc_busy",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hb_dout",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "fog_factor",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "des_comp_gen_fx": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dx_fx",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "in",
          "name": "dy_fx",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "in",
          "name": "cmp_i",
          "type": "wire",
          "width": "[95:0]"
        },
        {
          "direction": "out",
          "name": "curr_i",
          "type": "wire",
          "width": "[31:0]"
        }
      ],
      "fifo_267x128": [
        {
          "direction": "out",
          "name": "files",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": "[266:0]"
        },
        {
          "direction": "in",
          "name": "rdclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rdreq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wrclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wrreq",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[266:0]"
        },
        {
          "direction": "out",
          "name": "rdempty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wrempty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wrfull",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wrusedw",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "in",
          "name": "NODEFVAL",
          "type": "wire",
          "width": ""
        }
      ],
      "flt2int": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "afl",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "fx_int",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "flt_frac_test": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "afl",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "frac_flag",
          "type": "wire",
          "width": ""
        }
      ],
      "flt_fx_mult": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fx",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "in",
          "name": "bfl",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "fl",
          "type": "wire",
          "width": "[31:0]"
        }
      ],
      "flt_fx_rnd": [
        {
          "direction": "in",
          "name": "fp_in",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "int_out",
          "type": "wire",
          "width": "[31:0]"
        }
      ],
      "flt_fx_uv": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "float",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "fixed_out",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "vector",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s",
          "type": "wire",
          "width": "[4:0]"
        }
      ],
      "flt_recip_iter": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "denom",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "recip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "out",
          "name": "init_est",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "X0",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "flt_recip_rom": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "denom",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "recip",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "out",
          "name": "init_est",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "X0",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "graph_core": [
        {
          "direction": "in",
          "name": "hclock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "port",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pframen",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pirdyn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ptrdyn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pdevseln",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pidsel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pintan",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inout",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pgnntn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pcben",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "inout",
          "name": "pad",
          "type": "wire",
          "width": "[31:00]"
        },
        {
          "direction": "in",
          "name": "bios_rdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_wrn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_hld",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_wdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_xbuf",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_xbuf1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pll_sclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pll_sdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_dclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_de",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_data",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "dvo_bsel_scl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "dvo_dsel_sda",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ddc_scl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ddc_sda",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_psaven",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_cblankn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_csyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_sog",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_clko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "from",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_clki",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_field",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_hsyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_vsyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_blankn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_pal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_clk_sel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mb_32_sel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vga_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dual_enn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m66_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ledn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mictor_clke",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mictor_clko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mictor_de",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "mictor_do",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "gpio_3v",
          "type": "wire",
          "width": "[19:0]"
        },
        {
          "direction": "out",
          "name": "mem_odt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cs_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cke",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_addr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "out",
          "name": "mem_ba",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "mem_ras_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cas_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_we_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_dm",
          "type": "wire",
          "width": "[BYTES/4-1:0]"
        },
        {
          "direction": "inout",
          "name": "mem_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mem_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mem_dq",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "inout",
          "name": "mem_dqs",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "inout",
          "name": "mem_dqsn",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "pll_25_37p5",
          "type": "wire",
          "width": ""
        }
      ],
      "max_3d_top": [
        {
          "direction": "in",
          "name": "hclock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "port",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hresetn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pframen",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pirdyn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ptrdyn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pdevseln",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pidsel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pintan",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inout",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pgnntn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pcben",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "inout",
          "name": "pad",
          "type": "wire",
          "width": "[31:00]"
        },
        {
          "direction": "in",
          "name": "bios_rdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_wrn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_hld",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bios_wdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_clka",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_clkb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pll_sclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "pll_sdat",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mem_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mem_clk_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cke",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cs_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_odt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_ras_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_cas_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_we_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_ba",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "mem_addr",
          "type": "wire",
          "width": "[13:0]"
        },
        {
          "direction": "inout",
          "name": "mem_dq",
          "type": "wire",
          "width": "[63:0]"
        },
        {
          "direction": "inout",
          "name": "mem_dqs",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "inout",
          "name": "mem_dqsn",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "mem_dm",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "dvo_dclk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_hsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_vsync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_de",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dvo_data",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "dvo_bsel_scl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "dvo_dsel_sda",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ddc_scl",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "ddc_sda",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_psaven",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_cblankn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_csyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_sog",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_clko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "from",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_hsyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_vsyncn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_blankn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bt_field",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bt_pal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "t2r4_mode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mb_32_sel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "vga_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dual_enn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m66_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ledn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mictor_clke",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mictor_clko",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mictor_de",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "mictor_do",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "gpio_3v",
          "type": "wire",
          "width": "[19:0]"
        }
      ],
      "ram_tag": [
        {
          "direction": "in",
          "name": "de_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "de_rstn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cur_mipmap",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ee_s0_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ee_s1_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eo_s0_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eo_s1_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "oe_s0_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "oe_s1_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "oo_s0_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "oo_s1_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ee_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "eo_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "oe_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "oo_tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "ee_tag_adr_wr",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "eo_tag_adr_wr",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "oe_tag_adr_wr",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "oo_tag_adr_wr",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "ee_tag_dat_in",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "eo_tag_dat_in",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "oe_tag_dat_in",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "oo_tag_dat_in",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "tag_ram_csn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ee_tag_dat_out",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "eo_tag_dat_out",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "oe_tag_dat_out",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "out",
          "name": "oo_tag_dat_out",
          "type": "wire",
          "width": "[23:0]"
        },
        {
          "direction": "in",
          "name": "tag_s0_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tag_s1_loadn",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tag_adr_wr",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "tag_adr_rd",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "tag_dat_in",
          "type": "wire",
          "width": "[11:0]"
        },
        {
          "direction": "out",
          "name": "tag_dat_out",
          "type": "wire",
          "width": "[23:0]"
        }
      ],
      "sm_ref": [
        {
          "direction": "in",
          "name": "mem_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hreset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ref_gnt",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "svga_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "c_cr11_b6",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_c_crt_line_end",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ref_svga_req",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ref_req",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_t_ref_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ref_cycle_done",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "de3d_fog_table",
      "de3d_read_addr_in",
      "de3d_tfog",
      "des_comp_gen_fx",
      "fifo_267x128",
      "flt2int",
      "flt_frac_test",
      "flt_fx_mult",
      "flt_fx_rnd",
      "flt_fx_uv",
      "flt_recip_iter",
      "flt_recip_rom",
      "graph_core",
      "max_3d_top",
      "ram_tag",
      "sm_ref",
      "sv_log2"
    ]
  },
  {
    "namespace": "catalyst-neuromorphic",
    "name": "catalyst-n2",
    "latest": "583f9e012f66",
    "versions": [
      "583f9e012f66",
      "HEAD"
    ],
    "description": "Open-source neuromorphic processor (second generation) \u2014 LIF compartmental neurons, microcode learning, STDP + three-factor synaptic plasticity, asynchronous Network-on-Chip mesh, RV32I/RV32IM management cores, multi-chip routing. Apache-2.0, FPGA-validated on AWS F2, Kria, and Arty.",
    "license": "Apache-2.0",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/catalyst-neuromorphic/catalyst-n2.git",
    "tags": [
      "adapter",
      "asynchronous",
      "cluster",
      "converter",
      "interface",
      "neuromorphic",
      "protocol",
      "receiver",
      "scalable",
      "transmit",
      "transmitter",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-07T05:42:39Z",
    "updated_at": "2026-03-20T17:34:38+00:00",
    "desc_source": "verdict",
    "top_ports": {
      "axi_uart_bridge": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_neuro",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_neuro_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hi_rx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "hi_rx_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hi_tx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "hi_tx_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hi_tx_ready",
          "type": "wire",
          "width": ""
        }
      ],
      "multi_chip_router": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "my_chip_id",
          "type": "wire",
          "width": "[CHIP_ID_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_push",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_dest_chip",
          "type": "wire",
          "width": "[CHIP_ID_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_core",
          "type": "wire",
          "width": "[CORE_ID_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_neuron",
          "type": "wire",
          "width": "[NEURON_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "tx_payload",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "tx_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_src_chip",
          "type": "wire",
          "width": "[CHIP_ID_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_core",
          "type": "wire",
          "width": "[CORE_ID_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_neuron",
          "type": "wire",
          "width": "[NEURON_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "rx_current",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "rx_pop",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rx_empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "barrier_tx_send",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "barrier_rx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mgmt_tx_push",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mgmt_tx_core",
          "type": "wire",
          "width": "[CORE_ID_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "mgmt_tx_neuron",
          "type": "wire",
          "width": "[NEURON_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "mgmt_tx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "mgmt_tx_is_write",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mgmt_tx_dest_chip",
          "type": "wire",
          "width": "[CHIP_ID_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "mgmt_rx_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mgmt_rx_src_chip",
          "type": "wire",
          "width": "[CHIP_ID_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "mgmt_rx_core",
          "type": "wire",
          "width": "[CORE_ID_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "mgmt_rx_neuron",
          "type": "wire",
          "width": "[NEURON_BITS-1:0]"
        },
        {
          "direction": "out",
          "name": "mgmt_rx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "mgmt_rx_is_write",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "preempt_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "preempt_rx",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "link_tx_data",
          "type": "wire",
          "width": "[NUM_LINKS*8-1:0]"
        },
        {
          "direction": "out",
          "name": "link_tx_valid",
          "type": "wire",
          "width": "[NUM_LINKS-1:0]"
        },
        {
          "direction": "in",
          "name": "link_tx_ready",
          "type": "wire",
          "width": "[NUM_LINKS-1:0]"
        },
        {
          "direction": "in",
          "name": "link_rx_data",
          "type": "wire",
          "width": "[NUM_LINKS*8-1:0]"
        },
        {
          "direction": "in",
          "name": "link_rx_valid",
          "type": "wire",
          "width": "[NUM_LINKS-1:0]"
        },
        {
          "direction": "out",
          "name": "link_rx_ready",
          "type": "wire",
          "width": "[NUM_LINKS-1:0]"
        }
      ],
      "neuromorphic_top": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_rxd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart_txd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "link_tx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "link_tx_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "link_tx_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "link_rx_data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "link_rx_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "link_rx_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rx_data_ext",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "rx_valid_ext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "tx_data_ext",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "tx_valid_ext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tx_ready_ext",
          "type": "wire",
          "width": ""
        }
      ],
      "rv32im_cluster": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "imem_we_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "imem_waddr_0",
          "type": "wire",
          "width": "[IMEM_ADDR_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "imem_wdata_0",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "imem_we_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "imem_waddr_1",
          "type": "wire",
          "width": "[IMEM_ADDR_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "imem_wdata_1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "imem_we_2",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "imem_waddr_2",
          "type": "wire",
          "width": "[IMEM_ADDR_BITS-1:0]"
        },
        {
          "direction": "in",
          "name": "imem_wdata_2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "mmio_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mmio_we",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mmio_addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "mmio_wdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "mmio_rdata",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "mmio_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "halted",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "pc_out_0",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_out_1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_out_2",
          "type": "wire",
          "width": "[31:0]"
        }
      ]
    },
    "top_modules": [
      "axi_uart_bridge",
      "multi_chip_router",
      "neuromorphic_top",
      "rv32im_cluster"
    ]
  },
  {
    "namespace": "ctu-fee",
    "name": "ctucanfd_ip_core",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "CTU CAN FD is soft IP-Core written in VHDL which supports ISO and NON-ISO versions of CAN FD protocol.",
    "license": "MIT",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "ctu_can_fd_rtl",
    "source_url": "https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core.git",
    "tags": [
      "arbitrator",
      "calculator",
      "confinement",
      "high-performance",
      "measurement",
      "multiplexer",
      "reintegration",
      "retransmitt",
      "synchronisation",
      "synchronizer",
      "synchronous",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-10T14:35:58Z",
    "updated_at": "2026-01-07T13:55:29+01:00",
    "desc_source": "readme",
    "provides_packages": [
      "can_config_pkg",
      "can_constants_pkg",
      "can_fd_frame_format",
      "can_fd_register_map",
      "can_registers_pkg",
      "can_types_pkg",
      "cmn_reg_map_pkg"
    ],
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          "direction": "in",
          "name": "hresetn",
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        },
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          "direction": "in",
          "name": "hclk",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "haddr",
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          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "hwdata",
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          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "hsel",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hwrite",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "hsize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "hburst",
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          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "hprot",
          "type": "std_logic_vector",
          "width": "3 downto 0"
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          "direction": "in",
          "name": "htrans",
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          "width": "1 downto 0"
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        {
          "direction": "in",
          "name": "hmastlock",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "hready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hreadyout",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hresp",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "hrdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "res_n_out",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "can_tx",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "can_rx",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "timestamp",
          "type": "std_logic_vector",
          "width": "63 downto 0"
        },
        {
          "direction": "in",
          "name": "scan_enable",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "int",
          "type": "std_logic",
          "width": ""
        }
      ],
      "can_top_apb": [
        {
          "direction": "in",
          "name": "aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "arstn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scan_enable",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "res_n_out",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CAN_tx",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CAN_rx",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "timestamp",
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          "width": "63 downto 0"
        },
        {
          "direction": "in",
          "name": "s_apb_paddr",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_apb_penable",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_apb_pprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "s_apb_prdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "s_apb_pready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_apb_psel",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_apb_pslverr",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_apb_pstrb",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "s_apb_pwdata",
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          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_apb_pwrite",
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          "width": ""
        }
      ],
      "majority_decoder_3": [
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          "direction": "in",
          "name": "input",
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          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "output",
          "type": "std_logic",
          "width": ""
        }
      ],
      "memory_bus_template": [
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          "direction": "in",
          "name": "signal clk_sys",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal res_n",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal address",
          "type": "std_logic_vector",
          "width": "address_width - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "signal w_data",
          "type": "std_logic_vector",
          "width": "data_width - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "signal r_data",
          "type": "std_logic_vector",
          "width": "data_width - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "signal cs",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal read",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal write",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal be",
          "type": "std_logic_vector",
          "width": "data_width / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "signal lock_1",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal lock_2",
          "type": "std_logic",
          "width": ""
        }
      ],
      "shift_reg": [
        {
          "direction": "in",
          "name": "clk",
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          "width": ""
        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "input",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "reg_stat",
          "type": "std_logic_vector",
          "width": "G_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "reg_output",
          "type": "std_logic",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "can_top_ahb",
      "can_top_apb",
      "majority_decoder_3",
      "memory_bus_template",
      "shift_reg"
    ]
  },
  {
    "namespace": "enclustra",
    "name": "en_cl_fix_resize",
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    "versions": [
      "HEAD",
      "d2ce1a617bc8",
      "0.0.0"
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    "language": "vhdl-2008",
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      "fix",
      "resize"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-04-13T08:56:36+02:00",
    "package_deps": [
      "enclustra/en_cl_fix_round",
      "enclustra/en_cl_fix_saturate"
    ],
    "desc_source": "preserved",
    "provides_packages": [
      "en_cl_fix_pkg",
      "en_cl_fix_private_pkg"
    ],
    "top_ports": {
      "en_cl_fix_resize": [
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          "direction": "in",
          "name": "clk",
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          "width": ""
        },
        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "in_valid",
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          "width": ""
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        {
          "direction": "in",
          "name": "in_meta",
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          "width": "meta_width_g-1 downto 0"
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          "direction": "in",
          "name": "in_data",
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          "width": "cl_fix_width(in_fmt_g)-1 downto 0"
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        {
          "direction": "out",
          "name": "out_valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_meta",
          "type": "std_logic_vector",
          "width": "meta_width_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "out_data",
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          "width": "cl_fix_width(out_fmt_g)-1 downto 0"
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      ]
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      "saturate"
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  },
  {
    "namespace": "fpganinja",
    "name": "corundum",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Corundum 100G / 200G / 400G open-source NIC. Three subprojects: cndm_lite (DMA-lite), cndm_micro (microcoded engine), cndm_proto (prototype controller). Plus a board-level I2C controller.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
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    "tags": [
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      "completion",
      "control",
      "controller",
      "corundum",
      "datapath",
      "descriptor",
      "inter-integrated",
      "lightweight",
      "receiver",
      "transmit",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
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          "direction": "in",
          "name": "logic",
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        },
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          "direction": "snk",
          "name": "s_axis_cmd",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
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        }
      ],
      "cndm_lite_pcie_us": [
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        },
        {
          "direction": "out",
          "name": "delays",
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          "width": ""
        },
        {
          "direction": "snk",
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          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_cc",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_rq",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pcie_rc",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_brd_ctrl_cmd",
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          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_brd_ctrl_rsp",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "mac_axis_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_tx_cpl",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_rx",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ],
      "cndm_micro_pcie_us": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "delays",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pcie_cq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_cc",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_rq",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pcie_rc",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_brd_ctrl_cmd",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_brd_ctrl_rsp",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "mac_axis_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_tx_cpl",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_rx",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ],
      "cndm_proto_pcie_us": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pcie_cq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_cc",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pcie_rq",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pcie_rc",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "mac_axis_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_tx_cpl",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "mac_axis_rx",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "cndm_brd_ctrl_i2c",
      "cndm_lite_pcie_us",
      "cndm_micro_pcie_us",
      "cndm_proto_pcie_us"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "pyrite",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Pyrite PCIe configuration programmers \u2014 VPD (Vital Product Data) and VSEC (Vendor-Specific Extended Capability) over BPI flash and QSPI flash, UltraScale variants.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "bpi",
      "express",
      "pci",
      "pcie",
      "pyrite",
      "qspi",
      "us",
      "vpd",
      "vsec"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "pyrite_pcie_us_vpd_bpi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "enable",
          "type": "wire",
          "width": ""
        }
      ],
      "pyrite_pcie_us_vpd_qspi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "pyrite_pcie_us_vsec_bpi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "enable",
          "type": "wire",
          "width": ""
        }
      ],
      "pyrite_pcie_us_vsec_qspi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "pyrite_pcie_us_vpd_bpi",
      "pyrite_pcie_us_vpd_qspi",
      "pyrite_pcie_us_vsec_bpi",
      "pyrite_pcie_us_vsec_qspi"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-axi",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "AXI4 / AXI4-Lite / APB infrastructure: crossbars, interconnects, adapters, RAMs, registers, FIFOs, ties, AXI-internal DMA, arbiter.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "access",
      "adapter",
      "advanced",
      "arbiter",
      "arbitration",
      "converter",
      "crossbar",
      "datapath",
      "interconnect",
      "peripheral",
      "protocol",
      "register"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_apb_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_apb_axil_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_apb_dp_ram": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb_a",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb_b",
          "type": "taxi_apb_if.slv",
          "width": ""
        }
      ],
      "taxi_apb_interconnect": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dummy",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_apb_interconnect_1s": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dummy",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_apb_ram": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        }
      ],
      "taxi_apb_tie": [
        {
          "direction": "out",
          "name": "ADDR_W",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_axi_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_axil_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_cdma": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_crossbar": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_crossbar_1s": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_dma": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "rd_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "rd_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "wr_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "wr_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rd_data",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_wr_data",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_dp_ram": [
        {
          "direction": "out",
          "name": "port",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr_a",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd_a",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr_b",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd_b",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_axi_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_interconnect": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_interconnect_1s": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_ram": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_axi_register": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axi_tie": [
        {
          "direction": "wr_slv",
          "name": "s_axi_wr",
          "type": "taxi_axi_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axi_rd",
          "type": "taxi_axi_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_apb_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_axil_axi_adapter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_crossbar": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_crossbar_1s": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_dp_ram": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr_a",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd_a",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr_b",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd_b",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_axil_interconnect": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_interconnect_1s": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_ram": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_axil_register": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_axil_tie": [
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_apb_adapter",
      "taxi_apb_axil_adapter",
      "taxi_apb_dp_ram",
      "taxi_apb_interconnect",
      "taxi_apb_interconnect_1s",
      "taxi_apb_ram",
      "taxi_apb_tie",
      "taxi_axi_adapter",
      "taxi_axi_axil_adapter",
      "taxi_axi_cdma",
      "taxi_axi_crossbar",
      "taxi_axi_crossbar_1s",
      "taxi_axi_dma",
      "taxi_axi_dp_ram",
      "taxi_axi_fifo",
      "taxi_axi_interconnect",
      "taxi_axi_interconnect_1s",
      "taxi_axi_ram",
      "taxi_axi_register",
      "taxi_axi_tie",
      "taxi_axil_adapter",
      "taxi_axil_apb_adapter",
      "taxi_axil_axi_adapter",
      "taxi_axil_crossbar",
      "taxi_axil_crossbar_1s",
      "taxi_axil_dp_ram",
      "taxi_axil_interconnect",
      "taxi_axil_interconnect_1s",
      "taxi_axil_ram",
      "taxi_axil_register",
      "taxi_axil_tie"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-axis",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "AXI4-Stream infrastructure: FIFOs (sync/async/pipeline), broadcast, demux/mux, switch, register, COBS encode/decode, null src/snk, tie. Excludes Ethernet PCS streams (BASE-R, XGMII, GMII bridges) \u2014 those live in taxi-ethernet.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "adapter",
      "arbiter",
      "arbitration",
      "asynchronous",
      "bridge",
      "broadcast",
      "converter",
      "demultiplexer",
      "multiplexer",
      "pipeline",
      "protocol",
      "register"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_axis_arb_mux": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_async_fifo_adapter": [
        {
          "direction": "out",
          "name": "FIFO",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_broadcast": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_cobs_decode": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "final",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tdata_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_cobs_encode": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "if",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_concat": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_demux": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_fifo_adapter": [
        {
          "direction": "out",
          "name": "FIFO",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_mux": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_null_snk": [
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ],
      "taxi_axis_null_src": [
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_pad": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_pipeline_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_pipeline_register": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_switch": [
        {
          "direction": "out",
          "name": "interface",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_axis_tie": [
        {
          "direction": "snk",
          "name": "s_axis",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_axis_arb_mux",
      "taxi_axis_async_fifo_adapter",
      "taxi_axis_broadcast",
      "taxi_axis_cobs_decode",
      "taxi_axis_cobs_encode",
      "taxi_axis_concat",
      "taxi_axis_demux",
      "taxi_axis_fifo_adapter",
      "taxi_axis_mux",
      "taxi_axis_null_snk",
      "taxi_axis_null_src",
      "taxi_axis_pad",
      "taxi_axis_pipeline_fifo",
      "taxi_axis_pipeline_register",
      "taxi_axis_switch",
      "taxi_axis_tie"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-dma",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Generic DMA building blocks: AXIS client sink/source, descriptor mux, AXI-IF DMAs, DMA mux, ps-dpram (sync + async), RAM demux.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "access",
      "asynchronous",
      "client",
      "demultiplexer",
      "descriptor",
      "direct",
      "memory",
      "multiplexer",
      "psdpram",
      "random",
      "source",
      "stream"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_dma_client_axis_sink": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_wr_data",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_mst",
          "width": ""
        }
      ],
      "taxi_dma_client_axis_source": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rd_data",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_dma_if_axi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "rd_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "rd_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "wr_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "wr_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_dma_if_mux": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "client_rd_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "client_rd_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "client_wr_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "client_wr_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "req_src",
          "name": "dma_rd_req",
          "type": "taxi_dma_desc_if.req_src",
          "width": ""
        },
        {
          "direction": "sts_snk",
          "name": "dma_rd_sts",
          "type": "taxi_dma_desc_if.sts_snk",
          "width": ""
        },
        {
          "direction": "req_src",
          "name": "dma_wr_req",
          "type": "taxi_dma_desc_if.req_src",
          "width": ""
        },
        {
          "direction": "sts_snk",
          "name": "dma_wr_sts",
          "type": "taxi_dma_desc_if.sts_snk",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "client_ram_wr",
          "type": "taxi_dma_ram_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "client_ram_rd",
          "type": "taxi_dma_ram_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_dma_psdpram": [
        {
          "direction": "out",
          "name": "pipeline",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_dma_psdpram_async": [
        {
          "direction": "out",
          "name": "pipeline",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_wr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_wr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_rd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_rd",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_dma_ram_demux": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_slv",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "ram_wr",
          "type": "taxi_dma_ram_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "ram_rd",
          "type": "taxi_dma_ram_if.rd_mst",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_dma_client_axis_sink",
      "taxi_dma_client_axis_source",
      "taxi_dma_if_axi",
      "taxi_dma_if_mux",
      "taxi_dma_psdpram",
      "taxi_dma_psdpram_async",
      "taxi_dma_ram_demux"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-ethernet",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Full Ethernet stack: 1G/10G/25G MACs, 10G/25G PHYs, MII/GMII/RGMII PHY interfaces, MAC control + 802.3x pause, MDIO master, BASE-R + XGMII PCS encoders/decoders, transceiver reset helpers, eth_mac_stats.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "advanced",
      "controller",
      "ethernet",
      "independent",
      "interface",
      "management",
      "peripheral",
      "physical",
      "receiver",
      "synchronizer",
      "synchronous",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "health_tier": "gold",
    "contract_url": "https://github.com/routertl/ip-index/blob/main/contracts/eth_mac_1g_requirements.yml",
    "test_status_url": "https://github.com/routertl/ip-index/blob/main/test_results/fpganinja/taxi-ethernet/last_run.json",
    "last_verified_at": "2026-05-06",
    "desc_source": "curator",
    "top_ports": {
      "taxi_eth_mac_10g_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_1g_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_1g_gmii_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_1g_rgmii_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_25g_us": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb_ctrl",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "3",
          "name": "annex",
          "type": "802.3",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_mii_fifo": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rxd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "mii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mii_tx_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_txd",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "mii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mii_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_eth_mac_phy_10g_fifo": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_mdio_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_cmd",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rd_data",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_eth_mac_10g_fifo",
      "taxi_eth_mac_1g_fifo",
      "taxi_eth_mac_1g_gmii_fifo",
      "taxi_eth_mac_1g_rgmii_fifo",
      "taxi_eth_mac_25g_us",
      "taxi_eth_mac_mii_fifo",
      "taxi_eth_mac_phy_10g_fifo",
      "taxi_mdio_master"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-i2c",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "I2C master, slave (with APB / AXIL bridges), init engine, single-register peripheral.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "advanced",
      "amba",
      "axil",
      "circuit",
      "init",
      "inter-integrated",
      "master",
      "peripheral",
      "register",
      "si5340",
      "single",
      "slave"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "si5340_i2c_init": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "d",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_cmd",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_i2c_init": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[6:0]"
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "d",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_cmd",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_i2c_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_cmd",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_i2c_single_reg": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_i2c_slave_apb_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_i2c_slave_axil_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "si5340_i2c_init",
      "taxi_i2c_init",
      "taxi_i2c_master",
      "taxi_i2c_single_reg",
      "taxi_i2c_slave_apb_master",
      "taxi_i2c_slave_axil_master"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-pcie",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "PCIe AXI-Lite masters, MSI / MSI-X controllers, VPD / VSEC programmers, UltraScale/+ wrappers, PCIe-to-DMA bridges.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "access",
      "advanced",
      "amba",
      "axil",
      "direct",
      "express",
      "master",
      "memory",
      "minimal",
      "msix",
      "pcie",
      "peripheral"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_dma_if_pcie_us": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rq",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_rc",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "rd_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "rd_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "req_snk",
          "name": "wr_desc_req",
          "type": "taxi_dma_desc_if.req_snk",
          "width": ""
        },
        {
          "direction": "sts_src",
          "name": "wr_desc_sts",
          "type": "taxi_dma_desc_if.sts_src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "dma_ram_wr",
          "type": "taxi_dma_ram_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "dma_ram_rd",
          "type": "taxi_dma_ram_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_pcie_axil_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "rx_req_tlp",
          "type": "taxi_pcie_tlp_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "tx_cpl_tlp",
          "type": "taxi_pcie_tlp_if.src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_pcie_axil_master_minimal": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "rx_req_tlp",
          "type": "taxi_pcie_tlp_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "tx_cpl_tlp",
          "type": "taxi_pcie_tlp_if.src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_pcie_msix_apb": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_irq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "tx_wr_req_tlp",
          "type": "taxi_pcie_tlp_if.src",
          "width": ""
        }
      ],
      "taxi_pcie_msix_axil": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_irq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "tx_wr_req_tlp",
          "type": "taxi_pcie_tlp_if.src",
          "width": ""
        }
      ],
      "taxi_pcie_us_axil_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axis_cc_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_cq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_cc",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_pcie_us_cfg": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_pcie_us_msi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_pcie_us_vpd": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_pcie_us_vsec_apb": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axil_wr",
          "type": "taxi_axil_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axil_rd",
          "type": "taxi_axil_if.rd_mst",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_dma_if_pcie_us",
      "taxi_pcie_axil_master",
      "taxi_pcie_axil_master_minimal",
      "taxi_pcie_msix_apb",
      "taxi_pcie_msix_axil",
      "taxi_pcie_us_axil_master",
      "taxi_pcie_us_cfg",
      "taxi_pcie_us_msi",
      "taxi_pcie_us_vpd",
      "taxi_pcie_us_vsec_apb"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-ptp",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "PTP / IEEE-1588 clock, perout, time-domain APB / AXIL bridges.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "advanced",
      "amba",
      "axil",
      "clock",
      "crossing",
      "domain",
      "leaf",
      "peripheral",
      "perout",
      "precision",
      "protocol",
      "rel2tod"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_ptp_clock": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ptp_clock_cdc": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "if",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stepped",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "did",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "case",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pps_reg",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ptp_perout": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "from",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ptp_td_phc_apb": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "slv",
          "name": "s_apb",
          "type": "taxi_apb_if.slv",
          "width": ""
        }
      ],
      "taxi_ptp_td_phc_axil": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_ptp_td_rel2tod": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "path",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_ts_rel",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_ts_tod",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_ptp_clock",
      "taxi_ptp_clock_cdc",
      "taxi_ptp_perout",
      "taxi_ptp_td_phc_apb",
      "taxi_ptp_td_phc_axil",
      "taxi_ptp_td_rel2tod"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-ssio",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Source-synchronous I/O \u2014 DDR / SDR in / out with diff variants, plus the bare IDDR / ODDR I/O DDR-register primitives.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "data",
      "ddr",
      "diff",
      "double",
      "iddr",
      "memory",
      "oddr",
      "rate",
      "sdr",
      "ssio",
      "taxi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "ssio_sdr_in_diff": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ssio_ddr_in_diff": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ssio_ddr_out_diff": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ssio_sdr_out_diff": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "ssio_sdr_in_diff",
      "taxi_ssio_ddr_in_diff",
      "taxi_ssio_ddr_out_diff",
      "taxi_ssio_sdr_out_diff"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-uart",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "UART top + rx + tx primitives.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "asynchronous",
      "brg",
      "receive",
      "receiver",
      "rx",
      "serial",
      "taxi",
      "transmit",
      "transmitter",
      "tx",
      "uart",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_uart": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_uart"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-utils",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Standalone primitives without a project home: debounce, LFSR + CRC / PRBS / scramble variants, MT19937, IRQ rate-limit, LED shift-reg, MMCM fractional, RAM primitives, stats counters / strings, priority encoder, CDC synchronizers (reset + signal).",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "collect",
      "counter",
      "debounce",
      "descramble",
      "feedback",
      "interrupt",
      "mt19937",
      "redundancy",
      "register",
      "scramble",
      "synchronizer",
      "synchronous"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_debounce_switch": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "signals",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_irq_rate_limit": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_irq",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_irq",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_led_sreg": [
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_lfsr_crc": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_in_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CRC32C",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_lfsr_descramble": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "PRBS6",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_lfsr_prbs_check": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "PRBS6",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_lfsr_prbs_gen": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "PRBS6",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_lfsr_scramble": [
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "PRBS6",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_mmcm_frac": [
        {
          "direction": "in",
          "name": "input_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "output_offset_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "locked",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clocks",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "status",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_mt19937": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_penc": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bits",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ram_1r1w_1c": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ram_1r1w_2c": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ram_1rw": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ram_2rw_1c": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_ram_2rw_2c": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ],
      "taxi_stats_collect": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_stat",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_stats_counter": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_stat",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_stats_strings_full": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "mon",
          "name": "s_axis_stat",
          "type": "taxi_axis_if.mon",
          "width": ""
        },
        {
          "direction": "wr_slv",
          "name": "s_axil_wr",
          "type": "taxi_axil_if.wr_slv",
          "width": ""
        },
        {
          "direction": "rd_slv",
          "name": "s_axil_rd",
          "type": "taxi_axil_if.rd_slv",
          "width": ""
        }
      ],
      "taxi_sync_reset": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_debounce_switch",
      "taxi_irq_rate_limit",
      "taxi_led_sreg",
      "taxi_lfsr_crc",
      "taxi_lfsr_descramble",
      "taxi_lfsr_prbs_check",
      "taxi_lfsr_prbs_gen",
      "taxi_lfsr_scramble",
      "taxi_mmcm_frac",
      "taxi_mt19937",
      "taxi_penc",
      "taxi_ram_1r1w_1c",
      "taxi_ram_1r1w_2c",
      "taxi_ram_1rw",
      "taxi_ram_2rw_1c",
      "taxi_ram_2rw_2c",
      "taxi_stats_collect",
      "taxi_stats_counter",
      "taxi_stats_strings_full",
      "taxi_sync_reset"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "taxi-xfcp",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "XFCP debug protocol: UART transport, APB / AXI / AXIL / I2C-master modules, stats module, fabric switch.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "advanced",
      "asynchronous",
      "circuit",
      "inter-integrated",
      "master",
      "peripheral",
      "receiver",
      "serial",
      "stats",
      "switch",
      "transmitter",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "taxi_xfcp_if_uart": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "src",
          "name": "xfcp_dsp_ds",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "xfcp_dsp_us",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ],
      "taxi_xfcp_mod_apb": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xfcp_usp_us_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "xfcp_usp_ds",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "xfcp_usp_us",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "mst",
          "name": "m_apb",
          "type": "taxi_apb_if.mst",
          "width": ""
        }
      ],
      "taxi_xfcp_mod_axi": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "xfcp_usp_ds",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "xfcp_usp_us",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "wr_mst",
          "name": "m_axi_wr",
          "type": "taxi_axi_if.wr_mst",
          "width": ""
        },
        {
          "direction": "rd_mst",
          "name": "m_axi_rd",
          "type": "taxi_axi_if.rd_mst",
          "width": ""
        }
      ],
      "taxi_xfcp_mod_i2c_master": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "datapath",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xfcp_usp_us_tvalid_next",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "xfcp_usp_ds",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "xfcp_usp_us",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "taxi_xfcp_mod_stats": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "xfcp_usp_ds",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "xfcp_usp_us",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_stat",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "taxi_xfcp_if_uart",
      "taxi_xfcp_mod_apb",
      "taxi_xfcp_mod_axi",
      "taxi_xfcp_mod_i2c_master",
      "taxi_xfcp_mod_stats"
    ]
  },
  {
    "namespace": "fpganinja",
    "name": "zircon",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Zircon IP packet processor \u2014 RX parse / ingress / egress and TX buffer / deparse / ingress / egress, plus length+checksum core.",
    "license": "CERN-OHL-S-2.0",
    "license_class": "strong-copyleft",
    "language": "systemverilog",
    "library": "work",
    "source_url": "https://github.com/fpganinja/taxi.git",
    "tags": [
      "buffer",
      "deparse",
      "egress",
      "ingress",
      "internet",
      "network",
      "protocol",
      "receive",
      "receiver",
      "transmit",
      "transmitter",
      "zircon"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-04T01:08:52Z",
    "updated_at": "2026-05-12T13:06:02-07:00",
    "desc_source": "curator",
    "top_ports": {
      "zircon_ip_rx_egress": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pkt",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_ui_rx",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "zircon_ip_rx_ingress": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_mac_rx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pkt",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_meta_hdr",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_meta_len",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "zircon_ip_tx_buffer": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pkt_ui",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_meta_len",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pkt",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ],
      "zircon_ip_tx_egress": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_pkt",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_meta",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_mac_tx",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_mac_tx_cpl",
          "type": "taxi_axis_if.snk",
          "width": ""
        }
      ],
      "zircon_ip_tx_ingress": [
        {
          "direction": "in",
          "name": "logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "snk",
          "name": "s_axis_ui_tx",
          "type": "taxi_axis_if.snk",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_ui_tx_cpl",
          "type": "taxi_axis_if.src",
          "width": ""
        },
        {
          "direction": "src",
          "name": "m_axis_pkt",
          "type": "taxi_axis_if.src",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "zircon_ip_rx_egress",
      "zircon_ip_rx_ingress",
      "zircon_ip_tx_buffer",
      "zircon_ip_tx_egress",
      "zircon_ip_tx_ingress"
    ]
  },
  {
    "namespace": "lxp32",
    "name": "lxp32-cpu",
    "latest": "develop",
    "versions": [
      "develop"
    ],
    "description": "LXP32 is a small and FPGA friendly 32-bit CPU IP core based on a simple, original instruction set. Its key features include",
    "license": "MIT",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "work",
    "source_url": "https://github.com/lxp32/lxp32-cpu.git",
    "tags": [
      "decode",
      "digital",
      "divider",
      "execute",
      "interrupt",
      "mul16x16",
      "multiplexer",
      "processing",
      "processor",
      "ram256x32",
      "scratchpad",
      "shifter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-05T11:49:21Z",
    "updated_at": "2025-05-29T13:01:35+02:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-05",
    "desc_source": "readme",
    "top_ports": {
      "lxp32c_top": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ibus_cyc_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ibus_stb_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ibus_cti_o",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "ibus_bte_o",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "ibus_ack_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ibus_adr_o",
          "type": "std_logic_vector",
          "width": "29 downto 0"
        },
        {
          "direction": "in",
          "name": "ibus_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "dbus_cyc_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_stb_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_we_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_sel_o",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "dbus_ack_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_adr_o",
          "type": "std_logic_vector",
          "width": "31 downto 2"
        },
        {
          "direction": "out",
          "name": "dbus_dat_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "dbus_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "irq_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ],
      "lxp32u_top": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lli_re_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lli_adr_o",
          "type": "std_logic_vector",
          "width": "29 downto 0"
        },
        {
          "direction": "in",
          "name": "lli_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "lli_busy_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_cyc_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_stb_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_we_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_sel_o",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "dbus_ack_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbus_adr_o",
          "type": "std_logic_vector",
          "width": "31 downto 2"
        },
        {
          "direction": "out",
          "name": "dbus_dat_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "dbus_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "irq_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ]
    },
    "top_modules": [
      "lxp32c_top",
      "lxp32u_top"
    ]
  },
  {
    "namespace": "neorv32",
    "name": "neorv32",
    "latest": "f62ca4323d26",
    "versions": [
      "HEAD",
      "f62ca4323d26",
      "67fd919f88c6",
      "1c404050d68b",
      "d6260ef5a453",
      "0.0.0"
    ],
    "description": "The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** built around the NEORV32 [RISC-V](https://riscv.org/) CPU that is written in **platform-independent VHDL**.",
    "license": "BSD-3-Clause",
    "license_class": "permissive",
    "language": "vhdl-2008",
    "library": "neorv32",
    "source_url": "https://github.com/stnolting/neorv32.git",
    "tags": [
      "asynchronous",
      "bootloader",
      "converter",
      "decompressor",
      "interface",
      "modulation",
      "normalizer",
      "peripheral",
      "processor",
      "transmitter",
      "universal",
      "xbus2axi4"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-05-16T11:17:19+02:00",
    "desc_source": "readme",
    "provides_packages": [
      "neorv32_imem_image",
      "neorv32_package"
    ],
    "top_ports": {
      "neoTRNG_cell": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bus_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_bus_amo_rvs": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "b_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        }
      ],
      "neorv32_bus_gateway": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "b_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        }
      ],
      "neorv32_bus_io_switch": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "b_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        }
      ],
      "neorv32_bus_reg": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "b_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        }
      ],
      "neorv32_bus_switch": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "b_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        }
      ],
      "neorv32_clint_mtimecmp": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bus_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "time_o",
          "type": "std_ulogic_vector",
          "width": "63 downto 0"
        },
        {
          "direction": "out",
          "name": "mti_o",
          "type": "std_ulogic_vector",
          "width": "NUM_HARTS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "msi_o",
          "type": "std_ulogic_vector",
          "width": "NUM_HARTS-1 downto 0"
        }
      ],
      "neorv32_cpu_alu_fpu_f2i": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_i",
          "type": "ctrl_bus_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_addr_i",
          "type": "std_ulogic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "csr_wdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "csr_rdata_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "equal_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "less_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rs1_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "rs2_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "res_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "valid_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_cpu_alu_fpu_normalizer": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_i",
          "type": "ctrl_bus_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_addr_i",
          "type": "std_ulogic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "csr_wdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "csr_rdata_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "equal_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "less_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rs1_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "rs2_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "res_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "valid_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_cpu_frontend_ipb": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_i",
          "type": "ctrl_bus_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ibus_req_o",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ibus_rsp_i",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pmp_addr_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "pmp_priv_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pmp_err_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "frontend_o",
          "type": "if_bus_t",
          "width": ""
        }
      ],
      "neorv32_cpu_trace_simlog": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_i",
          "type": "ctrl_bus_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rs1_rdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "rs2_rdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_wdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "mem_ben_i",
          "type": "std_ulogic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "mem_addr_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "mem_wdata_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "trace_o",
          "type": "trace_port_t",
          "width": ""
        }
      ],
      "neorv32_gptmr_slice": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bus_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clkgen_i",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "irq_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_litex_core_complex": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tck_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tdi_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_tdo_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tms_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_adr_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_we_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_sel_o",
          "type": "std_ulogic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_stb_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_cyc_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_ack_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_err_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_mei_i",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_prim_fifo": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clear_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wdata_i",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "free_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "re_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdata_o",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "avail_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_prim_mul": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clear_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wdata_i",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "free_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "re_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdata_o",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "avail_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_prim_spram": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clear_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wdata_i",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "free_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "re_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdata_o",
          "type": "std_ulogic_vector",
          "width": "DWIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "avail_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_pwm_channel": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bus_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clkgen_i",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "pwm_o",
          "type": "std_ulogic_vector",
          "width": "31 downto 0"
        }
      ],
      "neorv32_sys_reset": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_ext_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_wdt_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_dbg_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rstn_ext_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rstn_sys_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xrstn_wdt_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xrstn_ocd_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_test_setup_approm": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_o",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        }
      ],
      "neorv32_test_setup_bootloader": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_o",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "uart0_txd_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rxd_i",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_test_setup_on_chip_debugger": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tck_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tdi_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_tdo_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tms_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_o",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "uart0_txd_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rxd_i",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_trng": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bus_req_i",
          "type": "bus_req_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bus_rsp_o",
          "type": "bus_rsp_t",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq_o",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_verilog_wrapper": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart0_txd_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rxd_i",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "neorv32_vivado_ip": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ocd_resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wdt_resetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_awaddr",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awlen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awsize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awburst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awcache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_wstrb",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_wlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_araddr",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arlen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arsize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arburst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arcache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "m_axi_arvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_arready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_rdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "m_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_axi_rlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_rvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_rready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_axi_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s0_axis_tdest",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "s0_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s0_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s0_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "s0_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s1_axis_tid",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "s1_axis_tvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s1_axis_tready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s1_axis_tdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s1_axis_tlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tck_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tdi_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_tdo_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_tms_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_dir_o",
          "type": "std_logic_vector",
          "width": "IO_GPIO_DIR_NUM-1 downto 0"
        },
        {
          "direction": "out",
          "name": "gpio_o",
          "type": "std_logic_vector",
          "width": "IO_GPIO_OUT_NUM-1 downto 0"
        },
        {
          "direction": "in",
          "name": "gpio_i",
          "type": "std_logic_vector",
          "width": "IO_GPIO_IN_NUM-1 downto 0"
        },
        {
          "direction": "out",
          "name": "uart0_txd_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_rxd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart0_rtsn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart0_ctsn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart1_txd_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart1_rxd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart1_rtsn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart1_ctsn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_clk_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_dat_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_dat_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_csn_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "sdi_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sdi_dat_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdi_dat_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sdi_csn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "twi_sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "twi_sda_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "twi_scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "twi_scl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "twd_sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "twd_sda_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "twd_scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "onewire_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "onewire_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_o",
          "type": "std_logic_vector",
          "width": "IO_PWM_NUM-1 downto 0"
        },
        {
          "direction": "in",
          "name": "cfs_in_i",
          "type": "std_logic_vector",
          "width": "255 downto 0"
        },
        {
          "direction": "out",
          "name": "cfs_out_o",
          "type": "std_logic_vector",
          "width": "255 downto 0"
        },
        {
          "direction": "out",
          "name": "neoled_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mtime_time_o",
          "type": "std_logic_vector",
          "width": "63 downto 0"
        },
        {
          "direction": "in",
          "name": "irq_msi_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_mti_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_mei_i",
          "type": "std_logic",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "neoTRNG_cell",
      "neorv32_bus_amo_rvs",
      "neorv32_bus_gateway",
      "neorv32_bus_io_switch",
      "neorv32_bus_reg",
      "neorv32_bus_switch",
      "neorv32_clint_mtimecmp",
      "neorv32_cpu_alu_fpu_f2i",
      "neorv32_cpu_alu_fpu_normalizer",
      "neorv32_cpu_frontend_ipb",
      "neorv32_cpu_trace_simlog",
      "neorv32_gptmr_slice",
      "neorv32_litex_core_complex",
      "neorv32_prim_fifo",
      "neorv32_prim_mul",
      "neorv32_prim_spram",
      "neorv32_pwm_channel",
      "neorv32_sys_reset",
      "neorv32_test_setup_approm",
      "neorv32_test_setup_bootloader",
      "neorv32_test_setup_on_chip_debugger",
      "neorv32_trng",
      "neorv32_verilog_wrapper",
      "neorv32_vivado_ip"
    ]
  },
  {
    "namespace": "ohwr",
    "name": "etherbone-core",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Etherbone \u2014 Wishbone-over-Ethernet remote-access protocol. Three HDL subsystems: Etherbone master (eb_master_core), slave (eb_slave_core, used by White Rabbit's wrc_core for remote register access), and a USB transport variant (eb_usb_core). OHWR-canonical post-migration.",
    "license": "LGPL-2.1",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "etherbone",
    "source_url": "https://gitlab.com/ohwr/project/etherbone-core.git",
    "tags": [
      "buffer",
      "checksum",
      "commit",
      "ethernet",
      "framer",
      "master",
      "multiplexer",
      "receive",
      "receiver",
      "transmit",
      "transmitter",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-07T08:21:24Z",
    "updated_at": "2025-04-09T14:43:47+02:00",
    "desc_source": "verdict",
    "external_uses": [
      {
        "library": "work",
        "package": "RandomPkg"
      },
      {
        "library": "work",
        "package": "genram_pkg"
      },
      {
        "library": "work",
        "package": "matrix_pkg"
      },
      {
        "library": "work",
        "package": "wishbone_pkg"
      },
      {
        "library": "work",
        "package": "wr_fabric_pkg"
      }
    ],
    "provides_packages": [
      "eb_hdr_pkg",
      "eb_internals_pkg",
      "ebm_auto_pkg",
      "etherbone_pkg",
      "ez_usb_pkg"
    ],
    "top_ports": {
      "eb_master_slave_wrapper": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "nRst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "snk_i",
          "type": "t_wrf_sink_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "snk_o",
          "type": "t_wrf_sink_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "src_o",
          "type": "t_wrf_source_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "src_i",
          "type": "t_wrf_source_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ebs_cfg_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ebs_cfg_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ebs_wb_master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ebs_wb_master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ebm_wb_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ebm_wb_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "eb_slave_core": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "nRst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "snk_i",
          "type": "t_wrf_sink_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "snk_o",
          "type": "t_wrf_sink_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "src_o",
          "type": "t_wrf_source_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "src_i",
          "type": "t_wrf_source_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cfg_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cfg_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        }
      ],
      "ez_usb": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "msi_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "msi_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rstn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ebcyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "speed_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "shift_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fifoadr_o",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "readyn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fulln_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "emptyn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sloen_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slrdn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slwrn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pktendn_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fd_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "fd_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "fd_oen_o",
          "type": "std_logic",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "eb_master_slave_wrapper",
      "eb_slave_core",
      "ez_usb"
    ]
  },
  {
    "namespace": "ohwr",
    "name": "general-cores",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "General Cores \u2014 generic FPGA primitive library. Edge detectors, CDC synchronizers (gc_sync_*), pulse synchronizer, debouncers, Wishbone primitives + slaves + crossbars (wb_*/xwb_*), generic memory primitives (genram_pkg single/dual-port + async FIFO), AXI/DSP/I2C primitives, 8b/10b coder, radiation-tolerant variants. The CERN BE-CO-HT primitive library underlying every OHWR design.",
    "license": "LGPL-2.1",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "general_cores",
    "source_url": "https://gitlab.com/ohwr/project/general-cores.git",
    "tags": [
      "arbitration",
      "asynchronous",
      "demodulator",
      "descrambler",
      "instruction",
      "integrators",
      "inter-integrated",
      "interconnect",
      "kintexultrascale",
      "multichannel",
      "synchronizer",
      "synchronizer2"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-07T08:21:24Z",
    "updated_at": "2026-05-08T07:43:51+00:00",
    "desc_source": "verdict",
    "external_uses": [
      {
        "library": "altera_mf",
        "package": "all"
      },
      {
        "library": "altera_mf",
        "package": "altera_mf_components"
      },
      {
        "library": "work",
        "package": "common_components"
      }
    ],
    "provides_packages": [
      "altera_networks_pkg",
      "axi4_pkg",
      "cm_wbgen2_pkg",
      "gc_cordic_pkg",
      "gc_dsp_pkg",
      "gencores_pkg",
      "genram_pkg",
      "memory_loader_pkg",
      "pcie_wb_pkg",
      "secded_32b_pkg",
      "spwm_wbgen2_pkg",
      "uart_wbgen2_pkg",
      "v6_fifo_pkg",
      "wb_fpgen_regs_pkg",
      "wb_irq_pkg",
      "wbconmax_pkg",
      "wbgen2_pkg",
      "wishbone_pkg",
      "xldr_wbgen2_pkg"
    ],
    "top_ports": {
      "altera_async_fifo": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_wr_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_almost_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_almost_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "clk_rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_almost_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_almost_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        }
      ],
      "altera_sync_fifo": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "almost_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "almost_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        }
      ],
      "axi4lite32_axi4full64_bridge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_awaddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awlen",
          "type": "STD_LOGIC_VECTOR",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awsize",
          "type": "STD_LOGIC_VECTOR",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awburst",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_awready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_wdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "63 downto 0"
        },
        {
          "direction": "in",
          "name": "s_wstrb",
          "type": "STD_LOGIC_VECTOR",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "s_wlast",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_wvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_wready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_bresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_bvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_bready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_araddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arlen",
          "type": "STD_LOGIC_VECTOR",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arsize",
          "type": "STD_LOGIC_VECTOR",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arburst",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_arready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_rdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "63 downto 0"
        },
        {
          "direction": "out",
          "name": "s_rresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_rlast",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_rvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_rready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_awaddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_awvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_awready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_wdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_wstrb",
          "type": "STD_LOGIC_VECTOR",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "m_wvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_wready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_bresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_bvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_araddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "m_arvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_arready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_rdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "m_rresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_rvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_rready",
          "type": "STD_LOGIC",
          "width": ""
        }
      ],
      "axi4lite_axi4full_bridge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_awaddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ADDR_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awlen",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_LEN_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awsize",
          "type": "STD_LOGIC_VECTOR",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awburst",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awid",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ID_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_awvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_awready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_wdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_DATA_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_wstrb",
          "type": "STD_LOGIC_VECTOR",
          "width": "(g_DATA_WIDTH / 8) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_wid",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ID_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_wlast",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_wvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_wready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_bid",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ID_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_bresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_bvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_bready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_araddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ADDR_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arlen",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_LEN_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arsize",
          "type": "STD_LOGIC_VECTOR",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arburst",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arid",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ID_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_arvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_arready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_rdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_DATA_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_rid",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ID_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_rresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_rlast",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_rvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_rready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_awaddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ADDR_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_awvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_awready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_wdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_DATA_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_wstrb",
          "type": "STD_LOGIC_VECTOR",
          "width": "(g_DATA_WIDTH / 8) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_wvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_wready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_bresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_bvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_araddr",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_ADDR_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "m_arvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_arready",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "in",
          "name": "m_rdata",
          "type": "STD_LOGIC_VECTOR",
          "width": "g_DATA_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_rresp",
          "type": "STD_LOGIC_VECTOR",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "m_rvalid",
          "type": "STD_LOGIC",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_rready",
          "type": "STD_LOGIC",
          "width": ""
        }
      ],
      "axi4lite_i2c_master": [
        {
          "direction": "in",
          "name": "s_axi_aclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_aresetn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_awaddr",
          "type": "std_logic_vector",
          "width": "C_S_AXI_ADDR_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_wdata",
          "type": "std_logic_vector",
          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wstrb",
          "type": "std_logic_vector",
          "width": "(C_S_AXI_DATA_WIDTH/8)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_araddr",
          "type": "std_logic_vector",
          "width": "C_S_AXI_ADDR_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "s_axi_arvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_arready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "s_axi_rdata",
          "type": "std_logic_vector",
          "width": "C_S_AXI_DATA_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "s_axi_rready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_scl_t",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i2c_sda_t",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "axi_gpio_expander": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "error_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gpio_out",
          "type": "std_logic_vector",
          "width": "g_num-1 downto 0"
        },
        {
          "direction": "in",
          "name": "gpio_oe",
          "type": "std_logic_vector",
          "width": "g_num-1 downto 0"
        },
        {
          "direction": "in",
          "name": "gpio_dir",
          "type": "std_logic_vector",
          "width": "g_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "gpio_in",
          "type": "std_logic_vector",
          "width": "g_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ARVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "AWVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ARADDR",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "AWADDR",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "WDATA",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "WSTRB",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "ARREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "AWREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "BVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RLAST",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "WREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "BRESP",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "RRESP",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "RDATA",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        }
      ],
      "cheby_dpssram": [
        {
          "direction": "in",
          "name": "clk_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_b_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr_a_i",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "addr_b_i",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "data_a_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "data_b_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "data_a_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "data_b_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "bwsel_a_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "bwsel_b_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rd_b_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_b_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "dec_8b10b_ctrl": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_10b_i",
          "type": "std_logic_vector",
          "width": "9 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "code_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdisp_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_8b_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ],
      "dec_8b10b_disp": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_10b_i",
          "type": "std_logic_vector",
          "width": "9 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "code_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdisp_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_8b_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ],
      "dec_8b10b_lut": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_10b_i",
          "type": "std_logic_vector",
          "width": "9 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "code_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdisp_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_8b_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ],
      "flash_top": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_ext_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_out_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_in_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_arbitrated_mux": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_num_inputs * g_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_valid_i",
          "type": "std_logic_vector",
          "width": "g_num_inputs-1 downto 0"
        },
        {
          "direction": "out",
          "name": "d_req_o",
          "type": "std_logic_vector",
          "width": "g_num_inputs-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_input_id_o",
          "type": "std_logic_vector",
          "width": "f_log2_ceil(g_num_inputs)-1 downto 0"
        }
      ],
      "gc_argb_led_drv": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "g_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "r_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "b_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dout_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ready_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "res_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_async_counter_diff": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_inc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_dec_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "inc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dec_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "counter_o",
          "type": "std_logic_vector",
          "width": "g_bits downto 0"
        }
      ],
      "gc_async_signals_input_stage": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signals_a_i",
          "type": "std_logic_vector",
          "width": "g_signal_num-1 downto 0"
        },
        {
          "direction": "in",
          "name": "config_active_i",
          "type": "std_logic_vector",
          "width": "g_signal_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "signals_o",
          "type": "std_logic_vector",
          "width": "g_signal_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "signals_p1_o",
          "type": "std_logic_vector",
          "width": "g_signal_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "signals_pN_o",
          "type": "std_logic_vector",
          "width": "g_signal_num-1 downto 0"
        }
      ],
      "gc_bicolor_led_ctrl": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "led_intensity_i",
          "type": "std_logic_vector",
          "width": "6 downto 0"
        },
        {
          "direction": "in",
          "name": "led_state_i",
          "type": "std_logic_vector",
          "width": "(g_nb_line * g_nb_column * 2) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "column_o",
          "type": "std_logic_vector",
          "width": "g_nb_column - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "line_o",
          "type": "std_logic_vector",
          "width": "g_nb_line - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "line_oen_o",
          "type": "std_logic_vector",
          "width": "g_nb_line - 1 downto 0"
        }
      ],
      "gc_cic": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ratio_sel_i",
          "type": "std_logic_vector",
          "width": "g_RATIO_SEL_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ratio_changed_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cic_combs": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ratio_sel_i",
          "type": "std_logic_vector",
          "width": "g_RATIO_SEL_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ratio_changed_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cic_decimator": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ratio_sel_i",
          "type": "std_logic_vector",
          "width": "g_RATIO_SEL_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ratio_changed_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cic_integrators": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ratio_sel_i",
          "type": "std_logic_vector",
          "width": "g_RATIO_SEL_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ratio_changed_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cic_ratio_change_detect": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ratio_sel_i",
          "type": "std_logic_vector",
          "width": "g_RATIO_SEL_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ratio_changed_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_comparator": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pol_inv_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "inp_i",
          "type": "std_logic_vector",
          "width": "g_IN_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "inn_i",
          "type": "std_logic_vector",
          "width": "g_IN_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "hys_i",
          "type": "std_logic_vector",
          "width": "g_IN_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "out_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_p_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cordic": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cor_mode_i",
          "type": "t_CORDIC_MODE",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cor_submode_i",
          "type": "t_CORDIC_SUBMODE",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lim_x_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lim_y_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x0_i",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "in",
          "name": "y0_i",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "in",
          "name": "z0_i",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "out",
          "name": "xn_o",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "out",
          "name": "yn_o",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "out",
          "name": "zn_o",
          "type": "std_logic_vector",
          "width": "g_M-1 downto 0"
        },
        {
          "direction": "out",
          "name": "lim_x_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lim_y_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rst_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_cordic_top": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mode_i",
          "type": "t_CORDIC_MODE",
          "width": ""
        },
        {
          "direction": "in",
          "name": "submode_i",
          "type": "t_CORDIC_SUBMODE",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_i",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "y_i",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "z_i",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lim_x_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lim_y_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_o",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y_o",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "z_o",
          "type": "std_logic_vector",
          "width": "g_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mode_o",
          "type": "t_CORDIC_MODE",
          "width": ""
        },
        {
          "direction": "out",
          "name": "submode_o",
          "type": "t_CORDIC_SUBMODE",
          "width": ""
        }
      ],
      "gc_crc_gen": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "en_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_i",
          "type": "std_logic_vector",
          "width": "g_data_width - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "restart_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "match_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "crc_o",
          "type": "std_logic_vector",
          "width": "g_polynomial'length - 1 downto 0"
        }
      ],
      "gc_dec_8b10b": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_10b_i",
          "type": "std_logic_vector",
          "width": "9 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "code_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rdisp_err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_8b_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ],
      "gc_delay_gen": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width - 1 downto 0"
        }
      ],
      "gc_ds182x_interface": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pps_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "onewire_b",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "id_o",
          "type": "std_logic_vector",
          "width": "63 downto 0"
        },
        {
          "direction": "out",
          "name": "temper_o",
          "type": "std_logic_vector",
          "width": "15 downto 0"
        },
        {
          "direction": "out",
          "name": "id_read_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "id_ok_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_dual_pi_controller": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_sysclk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "phase_err_i",
          "type": "std_logic_vector",
          "width": "g_error_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "phase_err_stb_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "freq_err_i",
          "type": "std_logic_vector",
          "width": "g_error_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "freq_err_stb_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mode_sel_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_val_o",
          "type": "std_logic_vector",
          "width": "g_dacval_bits-1 downto 0"
        },
        {
          "direction": "out",
          "name": "dac_val_stb_p_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_pcr_enable_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_pcr_force_f_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pll_fbgr_f_kp_i",
          "type": "std_logic_vector",
          "width": "g_coef_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "pll_fbgr_f_ki_i",
          "type": "std_logic_vector",
          "width": "g_coef_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "pll_pbgr_p_kp_i",
          "type": "std_logic_vector",
          "width": "g_coef_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "pll_pbgr_p_ki_i",
          "type": "std_logic_vector",
          "width": "g_coef_bits-1 downto 0"
        }
      ],
      "gc_dyn_extend_pulse": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pulse_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "len_i",
          "type": "std_logic_vector",
          "width": "g_len_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "extended_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_dyn_glitch_filt": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "len_i",
          "type": "std_logic_vector",
          "width": "g_len_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "dat_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dat_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_enc_8b10b": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_8b_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "err_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dispar_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dispar_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out_10b_o",
          "type": "std_logic_vector",
          "width": "9 downto 0"
        }
      ],
      "gc_freq_meas": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_freq_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_freq_ena_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "freq_low_thr_sys_i",
          "type": "std_logic_vector",
          "width": "g_COUNTER_WIDTH-1 downto 0"
        },
        {
          "direction": "in",
          "name": "freq_high_thr_sys_i",
          "type": "std_logic_vector",
          "width": "g_COUNTER_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_value_sys_o",
          "type": "std_logic_vector",
          "width": "g_COUNTER_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_value_freq_o",
          "type": "std_logic_vector",
          "width": "g_COUNTER_WIDTH-1 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_valid_sys_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "freq_valid_freq_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "freq_ok_sys_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "freq_ok_freq_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_frequency_meter": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_in_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pps_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "freq_o",
          "type": "std_logic_vector",
          "width": "g_COUNTER_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_valid_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_integer_divide": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "is_rem_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "is_signed_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_i",
          "type": "std_logic_vector",
          "width": "g_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "b_i",
          "type": "std_logic_vector",
          "width": "g_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "start_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ready_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "done_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_iq_demodulator": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adc_data_i",
          "type": "std_logic_vector",
          "width": "g_N-1 downto 0"
        },
        {
          "direction": "out",
          "name": "i_o",
          "type": "std_logic_vector",
          "width": "g_N downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_N downto 0"
        }
      ],
      "gc_iq_demodulator_shifted": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adc_data_i",
          "type": "std_logic_vector",
          "width": "g_N_data-1 downto 0"
        },
        {
          "direction": "in",
          "name": "phaseCos_i",
          "type": "std_logic_vector",
          "width": "g_N_coeff -1 downto 0"
        },
        {
          "direction": "in",
          "name": "phaseSin_i",
          "type": "std_logic_vector",
          "width": "g_N_coeff -1 downto 0"
        },
        {
          "direction": "out",
          "name": "i_o",
          "type": "std_logic_vector",
          "width": "g_N_data downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_N_data downto 0"
        }
      ],
      "gc_iq_modulator": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "en_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_i",
          "type": "std_logic_vector",
          "width": "g_N-1 downto 0"
        },
        {
          "direction": "in",
          "name": "q_i",
          "type": "std_logic_vector",
          "width": "g_N-1 downto 0"
        },
        {
          "direction": "out",
          "name": "i_o",
          "type": "std_logic_vector",
          "width": "g_N-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_N-1 downto 0"
        }
      ],
      "gc_moving_average": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "dout_o",
          "type": "std_logic_vector",
          "width": "g_data_width+g_avg_log2-1 downto 0"
        },
        {
          "direction": "out",
          "name": "dout_stb_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_multichannel_frequency_meter": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_in_i",
          "type": "std_logic_vector",
          "width": "g_CHANNELS -1 downto 0"
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pps_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "channel_sel_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_o",
          "type": "std_logic_vector",
          "width": "g_COUNTER_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "freq_valid_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_negedge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pulse_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_pi_regulator": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "en_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "setpoint_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "x_valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y_valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "y_o",
          "type": "std_logic_vector",
          "width": "g_OUTPUT_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "kp_i",
          "type": "std_logic_vector",
          "width": "g_GAIN_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "ki_i",
          "type": "std_logic_vector",
          "width": "g_GAIN_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "lim_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_pipelined_fir_filter": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "coefs_i",
          "type": "t_FIR_COEF_ARRAY",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_o",
          "type": "std_logic_vector",
          "width": "g_OUTPUT_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "d_valid_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_posedge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pulse_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_reset": [
        {
          "direction": "in",
          "name": "free_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "locked_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clks_i",
          "type": "std_logic_vector",
          "width": "g_clocks-1 downto 0"
        },
        {
          "direction": "out",
          "name": "rstn_o",
          "type": "std_logic_vector",
          "width": "g_clocks-1 downto 0"
        }
      ],
      "gc_reset_multi_aasd": [
        {
          "direction": "in",
          "name": "arst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clks_i",
          "type": "std_logic_vector",
          "width": "g_CLOCKS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "rst_n_o",
          "type": "std_logic_vector",
          "width": "g_CLOCKS-1 downto 0"
        }
      ],
      "gc_rr_arbiter": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "req_i",
          "type": "std_logic_vector",
          "width": "g_size-1 downto 0"
        },
        {
          "direction": "out",
          "name": "grant_o",
          "type": "std_logic_vector",
          "width": "g_size-1 downto 0"
        },
        {
          "direction": "out",
          "name": "grant_comb_o",
          "type": "std_logic_vector",
          "width": "g_size-1 downto 0"
        }
      ],
      "gc_scrambler_descrambler": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "aux_i",
          "type": "std_logic_vector",
          "width": "g_AUX_SIZE-1 downto 0"
        },
        {
          "direction": "in",
          "name": "data_i",
          "type": "std_logic_vector",
          "width": "g_DATA_SIZE-1 downto 0"
        },
        {
          "direction": "out",
          "name": "valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "aux_o",
          "type": "std_logic_vector",
          "width": "g_AUX_SIZE-1 downto 0"
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "std_logic_vector",
          "width": "g_DATA_SIZE-1 downto 0"
        }
      ],
      "gc_serial_dac": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "value_i",
          "type": "std_logic_vector",
          "width": "g_num_data_bits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "cs_sel_i",
          "type": "std_logic_vector",
          "width": "g_num_cs_select-1 downto 0"
        },
        {
          "direction": "in",
          "name": "load_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sclk_divsel_i",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "dac_cs_n_o",
          "type": "std_logic_vector",
          "width": "g_num_cs_select-1 downto 0"
        },
        {
          "direction": "out",
          "name": "dac_sclk_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dac_sdata_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dac_sel_i",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "busy_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_sfp_i2c_adapter": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sda_en_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_det_valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sfp_data_i",
          "type": "std_logic_vector",
          "width": "127 downto 0"
        }
      ],
      "gc_single_reset_gen": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_signals_n_a_i",
          "type": "std_logic_vector",
          "width": "g_rst_in_num-1 downto 0"
        },
        {
          "direction": "out",
          "name": "rst_n_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_soft_ramp_switch": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rate_i",
          "type": "std_logic_vector",
          "width": "15 downto 0"
        },
        {
          "direction": "in",
          "name": "on_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is_on_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is_off_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "busy_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x_valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x0_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "x1_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "x2_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "in",
          "name": "x3_i",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y_valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "y0_o",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y1_o",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y2_o",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        },
        {
          "direction": "out",
          "name": "y3_o",
          "type": "std_logic_vector",
          "width": "g_DATA_BITS-1 downto 0"
        }
      ],
      "gc_sync_word_rd": [
        {
          "direction": "in",
          "name": "clk_out_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_out_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_in_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_in_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_in_i",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_out_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ack_out_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_out_o",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "rd_in_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "gc_word_packer": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_input_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_valid_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_req_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "flush_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_output_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_valid_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_req_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "generic_async_fifo_mixedw": [
        {
          "direction": "in",
          "name": "rst_n_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_wr_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_wr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size * ((g_rd_width + g_wr_width - 1) / g_wr_width)) downto 0"
        },
        {
          "direction": "in",
          "name": "clk_rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_rd_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size * ((g_rd_width + g_wr_width - 1) / g_rd_width)) downto 0"
        }
      ],
      "generic_dpram_dualclock": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clka_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bwea_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wea_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "aa_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "da_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qa_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "clkb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bweb_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "web_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ab_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "db_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qb_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        }
      ],
      "generic_dpram_inst_7series": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clka_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bwea_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wea_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "aa_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "da_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qa_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "clkb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bweb_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "web_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ab_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "db_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qb_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        }
      ],
      "generic_dpram_sameclock": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bwea_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wea_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "aa_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "da_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qa_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "bweb_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "web_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ab_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "db_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "qb_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        }
      ],
      "generic_shiftreg_fifo": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "almost_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_valid_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "generic_spram": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bwe_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_i",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        }
      ],
      "lm32_cpu_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_cpu_medium": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
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        {
          "direction": "in",
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        },
        {
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          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
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        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "jtag_read_data",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
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        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
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        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
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        {
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          "name": "iram_i_adr_o",
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        {
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        {
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        {
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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        {
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        {
          "direction": "in",
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        {
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          "width": ""
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        {
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          "name": "iram_d_adr_o",
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          "width": "[31:0]"
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        {
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        {
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          "name": "iram_stall_request_x",
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        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
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        {
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
          "name": "I_SEL_O",
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          "width": "[ (4-1):0]"
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        {
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        {
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        {
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        {
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        },
        {
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        {
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        },
        {
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        {
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        {
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        {
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        {
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        },
        {
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        },
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        {
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        {
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        },
        {
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        {
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        {
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        {
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          "name": "stall_m",
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        {
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          "name": "kill_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "exception_m",
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        {
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          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_x",
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        },
        {
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          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
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        {
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        {
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          "width": ""
        },
        {
          "direction": "in",
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        {
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        {
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          "name": "load_q_m",
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          "width": ""
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        {
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          "name": "store_q_m",
          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "size_x",
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        },
        {
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        {
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          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
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        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
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          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "branch_offset",
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        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_cpu_medium_icache": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_cpu_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_cpu_minimal": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
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        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "icache_restart_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_cpu_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
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        {
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          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "name": "branch_offset",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
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          "width": "[31:0]"
        },
        {
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          "name": "iram_i_dat_i",
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        {
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          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
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      ],
      "lm32_dcache_full": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "D_ERR_I",
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          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
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        {
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          "name": "I_DAT_O",
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        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
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        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
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        },
        {
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          "name": "D_ADR_O",
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        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
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          "width": "[ (4-1):0]"
        },
        {
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          "name": "D_STB_O",
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        {
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        },
        {
          "direction": "out",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
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          "width": "[ (2-1):0]"
        },
        {
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          "name": "value",
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        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
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        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
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        {
          "direction": "in",
          "name": "modulus_d",
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        {
          "direction": "in",
          "name": "operand_0_d",
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        {
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          "name": "operand_1_d",
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        {
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          "name": "result_x",
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        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
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        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "stall_x",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
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          "width": "[1:0]"
        },
        {
          "direction": "in",
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          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_dcache_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_debug_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
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        },
        {
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        {
          "direction": "out",
          "name": "i_bte_o",
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        {
          "direction": "out",
          "name": "bus_error_d",
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        {
          "direction": "out",
          "name": "instruction_f",
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        },
        {
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        },
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        },
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        {
          "direction": "in",
          "name": "csr_write_data",
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        },
        {
          "direction": "out",
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        {
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        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
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        {
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          "name": "jtag_reg_addr_q",
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        {
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        {
          "direction": "out",
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        {
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          "name": "break_opcode",
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        {
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          "name": "bret",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
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        {
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        {
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          "name": "bp_match",
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          "name": "wp_match",
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        {
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        {
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        {
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        {
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        {
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        {
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        },
        {
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        {
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        {
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          "direction": "out",
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        {
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        {
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          "name": "trace_exception",
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          "width": ""
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        {
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        {
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          "name": "trace_eret",
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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          "direction": "in",
          "name": "stall_m",
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          "direction": "in",
          "name": "kill_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "exception_m",
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          "width": ""
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          "direction": "in",
          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
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        {
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          "width": ""
        },
        {
          "direction": "in",
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        {
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          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
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          "name": "store_q_m",
          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "size_x",
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          "direction": "in",
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
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        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
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          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_debug_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
        },
        {
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          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
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        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
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          "width": "[ (32-1):0]"
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          "name": "branch_offset",
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        {
          "direction": "out",
          "name": "load",
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          "width": ""
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          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
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          "width": ""
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        {
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          "name": "modulus",
          "type": "wire",
          "width": ""
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        {
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          "name": "branch",
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          "width": ""
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          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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          "direction": "in",
          "name": "address_a",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_debug_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_full": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
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        {
          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "read_enable_f",
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
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        {
          "direction": "out",
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          "type": "wire",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "direction": "in",
          "name": "kill_f",
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          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_x",
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        {
          "direction": "in",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
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          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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          "type": "wire",
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          "direction": "out",
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          "direction": "out",
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          "direction": "out",
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "i_we_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
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          "width": "[31:0]"
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        {
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          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
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          "type": "wire",
          "width": ""
        },
        {
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          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
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        {
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          "name": "dflush",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
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        {
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          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
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        {
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          "width": ""
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        {
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          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
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          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
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        },
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          "width": ""
        },
        {
          "direction": "in",
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          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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        },
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          "direction": "out",
          "name": "interrupt_exception",
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          "direction": "out",
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
          "name": "jtag_reg_q",
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        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
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          "width": "[2:0]"
        },
        {
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
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        {
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        },
        {
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          "name": "jtag_csr_write_data",
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        {
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
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        {
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          "name": "q_x",
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          "width": ""
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        {
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          "name": "dc_ss",
          "type": "wire",
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        {
          "direction": "out",
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          "type": "wire",
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        {
          "direction": "out",
          "name": "bp_match",
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        },
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          "name": "wp_match",
          "type": "wire",
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        {
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "direction": "out",
          "name": "jtag_reset",
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          "direction": "in",
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          "direction": "in",
          "name": "debug_exception",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "trace_exception",
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          "width": ""
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        {
          "direction": "out",
          "name": "trace_eid",
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        {
          "direction": "out",
          "name": "trace_eret",
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        {
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          "name": "trace_bret",
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        {
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        {
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        {
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          "direction": "out",
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
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        {
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        {
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        {
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        {
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          "direction": "in",
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          "width": ""
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          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
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        {
          "direction": "in",
          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
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          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
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          "width": ""
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        {
          "direction": "in",
          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
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          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_medium_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_medium_icache": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
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          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
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          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "D_CTI_O",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
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        },
        {
          "direction": "in",
          "name": "exception",
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        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
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          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
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        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
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          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_d",
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        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
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        {
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          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
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          "direction": "out",
          "name": "wp_match",
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        {
          "direction": "in",
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        {
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          "width": "[ (32-1):0]"
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        {
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        {
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        {
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        {
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          "name": "jtx_csr_read_data",
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        {
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          "name": "jrx_csr_read_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
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          "direction": "out",
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          "direction": "in",
          "name": "debug_exception",
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          "width": ""
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          "type": "wire",
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        {
          "direction": "in",
          "name": "enable_i",
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          "width": ""
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          "direction": "out",
          "name": "trace_pc",
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          "direction": "out",
          "name": "trace_pc_valid",
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        {
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          "name": "trace_exception",
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          "width": ""
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        {
          "direction": "out",
          "name": "trace_eid",
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          "width": "[ (3-1):0]"
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        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
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          "name": "iram_d_dat_o",
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        {
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          "width": ""
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "width": "[ (5-1):0]"
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        {
          "direction": "out",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": ""
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        {
          "direction": "out",
          "name": "iram_d_adr_o",
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          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "iram_d_dat_i",
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          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "iram_stall_request_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
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      "lm32_decoder_medium_icache_debug": [
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          "direction": "in",
          "name": "clk_i",
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          "width": ""
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        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
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        {
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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          "name": "D_DAT_I",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "I_WE_O",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
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        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
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          "width": "[ (2-1):0]"
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        {
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        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
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        },
        {
          "direction": "out",
          "name": "D_WE_O",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
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        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
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          "name": "value",
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        {
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        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "direction": "in",
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          "type": "wire",
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        {
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        {
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        {
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          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
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          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
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          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
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          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
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        {
          "direction": "out",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
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          "direction": "out",
          "name": "refilling",
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
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          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
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        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
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          "width": "[ 7:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
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        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
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          "width": "[ 7:0]"
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "width": "[ (3-1):0]"
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        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
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        {
          "direction": "out",
          "name": "iram_i_adr_o",
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        {
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        {
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_minimal": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_decoder_wr_node": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_icache_full": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "name": "load_store_address_w",
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        {
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        },
        {
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          "width": ""
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        {
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          "name": "load_q_x",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_1",
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          "width": "[ (5-1):0]"
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        {
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        {
          "direction": "out",
          "name": "write_idx",
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          "width": "[ (5-1):0]"
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        {
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          "name": "immediate",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "size",
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        {
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          "name": "sign_extend",
          "type": "wire",
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          "name": "adder_op",
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          "width": ""
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        {
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          "name": "logic_op",
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          "width": "[ 3:0]"
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        {
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          "name": "divide",
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          "name": "modulus",
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        {
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        {
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          "name": "branch_reg",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "condition",
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          "width": "[ (3-1):0]"
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        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "scall",
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          "width": ""
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        {
          "direction": "out",
          "name": "eret",
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "refilling",
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          "direction": "out",
          "name": "inst",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "store_byte_select",
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          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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          "direction": "out",
          "name": "pc_m",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "icache_stall_request",
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          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
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          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
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        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
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        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_icache_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_icache_medium_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_icache_medium_icache": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
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        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
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        },
        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
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          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
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        {
          "direction": "out",
          "name": "iram_i_adr_o",
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        },
        {
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          "name": "iram_d_dat_o",
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        },
        {
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        {
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        {
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        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
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          "width": ""
        },
        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "dbg_break_i",
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          "width": ""
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        {
          "direction": "out",
          "name": "iram_d_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
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          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "iram_stall_request_x",
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        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
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          "width": ""
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      "lm32_icache_medium_icache_debug": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "interrupt",
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        {
          "direction": "in",
          "name": "I_DAT_I",
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        {
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        {
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        {
          "direction": "in",
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          "name": "D_DAT_I",
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        {
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
          "name": "I_SEL_O",
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          "width": "[ (4-1):0]"
        },
        {
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "I_BTE_O",
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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        },
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          "name": "value",
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        {
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
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          "width": "[ (32-1):0]"
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        {
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        {
          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "stall_x",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_full": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
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          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_medium": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_medium_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_medium_icache": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_instruction_unit_minimal": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
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        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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        },
        {
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          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "i_we_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
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        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
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        {
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          "name": "exception",
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        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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        },
        {
          "direction": "out",
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        {
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        {
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        {
          "direction": "in",
          "name": "jtag_update",
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          "name": "jtag_reg_q",
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        {
          "direction": "in",
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        {
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        {
          "direction": "out",
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        {
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        {
          "direction": "out",
          "name": "bret",
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          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
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        {
          "direction": "in",
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        {
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        {
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        {
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          "name": "jtag_csr",
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        {
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        {
          "direction": "in",
          "name": "exception_x",
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        {
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          "name": "q_x",
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
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        {
          "direction": "out",
          "name": "wp_match",
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
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          "direction": "out",
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        {
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        {
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        {
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        {
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          "name": "trace_eret",
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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          "direction": "in",
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          "direction": "in",
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          "width": "[ (32-1):0]"
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        {
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          "type": "wire",
          "width": ""
        },
        {
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        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
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          "name": "store_q_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
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        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
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          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "branch_offset",
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          "direction": "out",
          "name": "load",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
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          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
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          "width": ""
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
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          "width": ""
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        {
          "direction": "out",
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        {
          "direction": "out",
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          "direction": "out",
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        {
          "direction": "out",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "address_m",
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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        {
          "direction": "out",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "direction": "in",
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          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
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        },
        {
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        {
          "direction": "out",
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        {
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        {
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          "width": ""
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        {
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "bus_error_d",
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          "width": ""
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        {
          "direction": "out",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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        },
        {
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        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
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          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
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          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
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          "width": "[ 7:0]"
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        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
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          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_d",
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          "width": "[ 7:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
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          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
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          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
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          "width": "[ (5-1):0]"
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "width": "[ 7:0]"
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
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          "width": "[ 7:0]"
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        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_pc",
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_eid",
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          "width": "[ (3-1):0]"
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        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "trace_bret",
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        {
          "direction": "out",
          "name": "iram_i_adr_o",
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        {
          "direction": "out",
          "name": "iram_d_dat_o",
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        {
          "direction": "in",
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        {
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          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "iram_d_en_o",
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          "width": ""
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        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
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      ],
      "lm32_interrupt_full": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "interrupt",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "I_DAT_I",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
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        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
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        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "D_DAT_I",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
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        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
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          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
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        {
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          "name": "iram_i_adr_o",
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        {
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          "name": "iram_d_dat_o",
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        {
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        {
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        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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        },
        {
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        {
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          "name": "dbg_reset_i",
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        {
          "direction": "in",
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          "width": ""
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        {
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          "name": "iram_d_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
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        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
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          "width": ""
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      ],
      "lm32_interrupt_full_debug": [
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          "name": "clk_i",
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        {
          "direction": "in",
          "name": "rst_i",
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        {
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          "name": "interrupt",
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          "direction": "in",
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        },
        {
          "direction": "in",
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        {
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        {
          "direction": "in",
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        {
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        {
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        {
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        {
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        },
        {
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          "width": ""
        },
        {
          "direction": "out",
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        },
        {
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        {
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        {
          "direction": "out",
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        {
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        },
        {
          "direction": "out",
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        {
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        {
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        },
        {
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        },
        {
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        {
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        {
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        {
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        {
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        },
        {
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        },
        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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          "name": "kill_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "exception_m",
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        {
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          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
        },
        {
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        },
        {
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          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
        },
        {
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        {
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        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
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        {
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "size_x",
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        },
        {
          "direction": "in",
          "name": "dflush",
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        },
        {
          "direction": "in",
          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "d_ack_i",
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          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "branch_offset",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "exception",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
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          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_d",
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        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
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          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
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          "width": "[ (5-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
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          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
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        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
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        {
          "direction": "out",
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          "width": "[31:0]"
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        {
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          "name": "iram_i_dat_i",
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          "width": "[31:0]"
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        {
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          "name": "iram_d_sel_o",
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          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "iram_d_en_o",
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          "width": ""
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        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
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      "lm32_interrupt_medium": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_interrupt_medium_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_interrupt_medium_icache": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
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        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
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        {
          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
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          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
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          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
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        },
        {
          "direction": "in",
          "name": "kill_f",
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          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
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        },
        {
          "direction": "in",
          "name": "i_ack_i",
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
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        {
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        {
          "direction": "out",
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
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        {
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        {
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": ""
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        {
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        },
        {
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          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
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          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "instruction_f",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "instruction_d",
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        },
        {
          "direction": "in",
          "name": "exception",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
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          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
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          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
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          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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        {
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          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_interrupt_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_interrupt_minimal": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_interrupt_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_jtag_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_jtag_medium_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_jtag_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
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        },
        {
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          "width": ""
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        {
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          "type": "wire",
          "width": ""
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        {
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          "width": ""
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        {
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          "name": "stall_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_w",
          "type": "wire",
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        {
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        {
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          "width": ""
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        {
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        },
        {
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          "name": "store_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "store_q_m",
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          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
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          "name": "size_x",
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          "width": "[ 1:0]"
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          "name": "dflush",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
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        {
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          "type": "wire",
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        {
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          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "load_data_w",
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          "width": "[ (32-1):0]"
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        {
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        {
          "direction": "out",
          "name": "d_dat_o",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
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        {
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        {
          "direction": "out",
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          "width": "[ (4-1):0]"
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
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          "name": "instruction",
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          "width": "[ (32-1):0]"
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        {
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          "width": "[ 0:0]"
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        {
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          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
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          "name": "x_result_sel_csr",
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        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
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        {
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        {
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          "name": "x_result_sel_add",
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          "width": ""
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        {
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          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
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        {
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          "name": "w_result_sel_load",
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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          "direction": "out",
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          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
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          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
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          "width": "[ (5-1):0]"
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          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_1",
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          "width": "[ (5-1):0]"
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        {
          "direction": "out",
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          "width": "[ (5-1):0]"
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          "name": "immediate",
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          "name": "store",
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          "width": ""
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        {
          "direction": "out",
          "name": "size",
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          "width": "[ 1:0]"
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          "name": "sign_extend",
          "type": "wire",
          "width": ""
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          "name": "adder_op",
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          "width": ""
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          "name": "logic_op",
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          "width": "[ 3:0]"
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        {
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          "direction": "out",
          "name": "condition",
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          "width": "[ (3-1):0]"
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          "name": "bi_unconditional",
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          "width": ""
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          "name": "scall",
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          "width": ""
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          "direction": "out",
          "name": "eret",
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          "width": ""
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          "name": "valid_d",
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          "direction": "in",
          "name": "branch_predict_taken_d",
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          "direction": "in",
          "name": "read_enable_f",
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
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          "width": ""
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
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          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "inst",
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          "width": "[ (32-1):0]"
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          "direction": "in",
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          "type": "wire",
          "width": "[ (32-1):0]"
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          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "direction": "in",
          "name": "store_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "store_byte_select",
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          "width": "[ (4-1):0]"
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          "direction": "out",
          "name": "load_data",
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          "width": "[ (32-1):0]"
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          "direction": "in",
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          "direction": "in",
          "name": "kill_f",
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          "direction": "in",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
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          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
          "name": "branch_taken_m",
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
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          "width": ""
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          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
          "name": "i_dat_i",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_m",
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          "direction": "out",
          "name": "icache_stall_request",
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          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
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          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
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        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
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        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
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        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
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          "direction": "in",
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          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
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        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_full": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_medium": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
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        {
          "direction": "out",
          "name": "instruction_f",
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          "width": "[ (32-1):0]"
        },
        {
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        },
        {
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        },
        {
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          "name": "eret_q_x",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
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        {
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          "name": "jtag_reg_addr_q",
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        },
        {
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        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
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        {
          "direction": "out",
          "name": "break_opcode",
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        {
          "direction": "out",
          "name": "bret",
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        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "csr_x",
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        {
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        {
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        {
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        {
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        {
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        {
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          "name": "q_x",
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        {
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          "name": "dc_ss",
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        {
          "direction": "out",
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        {
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          "name": "bp_match",
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          "direction": "out",
          "name": "wp_match",
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        {
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        {
          "direction": "in",
          "name": "jtag_write_data",
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        {
          "direction": "in",
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        {
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        {
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        {
          "direction": "in",
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          "width": ""
        },
        {
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          "name": "jtx_csr_read_data",
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        {
          "direction": "out",
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        {
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          "direction": "out",
          "name": "jtag_reset",
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          "direction": "in",
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        },
        {
          "direction": "in",
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          "name": "trace_pc",
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        {
          "direction": "out",
          "name": "trace_pc_valid",
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        {
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          "name": "trace_exception",
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          "width": ""
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        {
          "direction": "out",
          "name": "trace_eid",
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        {
          "direction": "out",
          "name": "trace_eret",
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        {
          "direction": "out",
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
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        {
          "direction": "out",
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        },
        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
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        {
          "direction": "in",
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        {
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        {
          "direction": "in",
          "name": "stall_m",
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
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          "width": "[1:0]"
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
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        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
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          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
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          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_medium_icache": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
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        {
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          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "name": "divide_by_zero_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
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        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
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          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
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          "width": "[ (32-1):0]"
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          "name": "load",
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          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
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          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
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          "width": "[ 3:0]"
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        {
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          "name": "direction",
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        {
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          "name": "divide",
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          "name": "modulus",
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        {
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          "name": "branch",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
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        {
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          "name": "bi_conditional",
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          "width": ""
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          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
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          "name": "scall",
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          "width": ""
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        {
          "direction": "out",
          "name": "eret",
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          "width": ""
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          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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          "name": "address_a",
          "type": "wire",
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          "direction": "in",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
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          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "valid_f",
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_x",
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_minimal": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_load_store_unit_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
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        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
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          "width": ""
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        {
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          "name": "I_DAT_O",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
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          "type": "wire",
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        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
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          "width": "[ (3-1):0]"
        },
        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
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          "width": "[ (2-1):0]"
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        {
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          "name": "value",
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          "width": ""
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        {
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          "width": ""
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        {
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          "name": "modulus_d",
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        {
          "direction": "in",
          "name": "operand_0_d",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
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          "width": ""
        },
        {
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          "name": "stall_x",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
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        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
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        {
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        {
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        {
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          "width": ""
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        {
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          "width": ""
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        {
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          "name": "load_q_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
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        {
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          "name": "dflush",
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        {
          "direction": "in",
          "name": "d_dat_i",
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          "width": "[ (32-1):0]"
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        {
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        {
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        {
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          "name": "d_rty_i",
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          "width": ""
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          "width": ""
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        {
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          "width": ""
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        {
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          "type": "wire",
          "width": ""
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        {
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          "name": "load_data_w",
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          "width": "[ (32-1):0]"
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        {
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          "type": "wire",
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        {
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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        {
          "direction": "out",
          "name": "d_sel_o",
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          "width": "[ (4-1):0]"
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "d_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "d_bte_o",
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          "width": "[ (2-1):0]"
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        {
          "direction": "in",
          "name": "instruction",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_m",
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          "name": "pc_w",
          "type": "wire",
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        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
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          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
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        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "iram_i_adr_o",
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          "width": "[31:0]"
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        {
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          "name": "iram_d_dat_o",
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        {
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        {
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        {
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        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
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        {
          "direction": "in",
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        {
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          "width": ""
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        {
          "direction": "out",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
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        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
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        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
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      "lm32_mc_arithmetic_full": [
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          "name": "clk_i",
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        {
          "direction": "in",
          "name": "rst_i",
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        {
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          "name": "interrupt",
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        },
        {
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        {
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          "type": "wire",
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        {
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        {
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        {
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
          "name": "I_SEL_O",
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          "width": "[ (4-1):0]"
        },
        {
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "I_BTE_O",
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          "width": "[ (2-1):0]"
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        {
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        {
          "direction": "out",
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        },
        {
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        },
        {
          "direction": "out",
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        {
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": "[ (2-1):0]"
        },
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          "name": "value",
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          "direction": "in",
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        {
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        {
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          "name": "operand_1_d",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
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          "type": "wire",
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        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
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          "width": "[1:0]"
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_mc_arithmetic_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_mc_arithmetic_medium": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
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        {
          "direction": "in",
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        },
        {
          "direction": "in",
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        },
        {
          "direction": "in",
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          "direction": "out",
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        {
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        {
          "direction": "out",
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
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        {
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        {
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        {
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        {
          "direction": "out",
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        {
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        {
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        {
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          "direction": "in",
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        {
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        {
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          "width": ""
        },
        {
          "direction": "in",
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        {
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        {
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          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "size_x",
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        },
        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
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          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
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        {
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        {
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        {
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          "name": "x_result_sel_csr",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
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        {
          "direction": "out",
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          "width": ""
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        {
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          "name": "x_result_sel_logic",
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          "width": ""
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        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
          "name": "read_idx_0",
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        {
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        {
          "direction": "out",
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        {
          "direction": "out",
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        {
          "direction": "out",
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          "direction": "out",
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        {
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          "direction": "out",
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        {
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        {
          "direction": "out",
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        },
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          "direction": "out",
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          "direction": "in",
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          "width": ""
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        {
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        {
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        {
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        {
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        {
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "width": ""
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        {
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          "width": "[31:0]"
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        {
          "direction": "in",
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        {
          "direction": "out",
          "name": "iram_stall_request_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
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      "lm32_mc_arithmetic_medium_icache": [
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        {
          "direction": "in",
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        {
          "direction": "in",
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        {
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        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
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        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
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          "width": "[2:0]"
        },
        {
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          "name": "jtag_reg_d",
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        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
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          "width": "[ (5-1):0]"
        },
        {
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          "width": ""
        },
        {
          "direction": "in",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "jtag_csr",
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        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "jtag_read_enable",
          "type": "wire",
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        },
        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
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        },
        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
        },
        {
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        },
        {
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        {
          "direction": "in",
          "name": "exception_q_w",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
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        {
          "direction": "out",
          "name": "jtag_reset",
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          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
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          "width": ""
        },
        {
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          "width": ""
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        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
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        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
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        {
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          "name": "iram_i_adr_o",
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        {
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          "name": "iram_d_dat_o",
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        {
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        {
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        {
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          "name": "dbg_csr_write_enable_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
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        },
        {
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          "name": "dbg_csr_addr_i",
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        },
        {
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        {
          "direction": "in",
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        {
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          "width": ""
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        {
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          "width": "[31:0]"
        },
        {
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        {
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          "name": "iram_stall_request_x",
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        },
        {
          "direction": "out",
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      "lm32_mc_arithmetic_medium_icache_debug": [
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          "direction": "in",
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          "direction": "in",
          "name": "rst_i",
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          "name": "interrupt",
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        {
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        {
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        {
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        {
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        },
        {
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        {
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        {
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        {
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        },
        {
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        },
        {
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        {
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        },
        {
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        {
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        {
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        {
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        {
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        {
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          "name": "value",
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        {
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        {
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        {
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        {
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        {
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        {
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          "name": "stall_m",
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
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        {
          "direction": "in",
          "name": "exception_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "store_operand_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_m",
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          "width": "[ (32-1):0]"
        },
        {
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        },
        {
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        },
        {
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          "type": "wire",
          "width": ""
        },
        {
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        },
        {
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        },
        {
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          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "store_q_m",
          "type": "wire",
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
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        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
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          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_mc_arithmetic_minimal": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "load",
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "size",
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          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
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          "width": ""
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        {
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          "name": "modulus",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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        {
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          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_mc_arithmetic_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[`LM32_INTERRUPT_RNG]"
        },
        {
          "direction": "in",
          "name": "user_result",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "in",
          "name": "user_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "user_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "user_opcode",
          "type": "wire",
          "width": "[`LM32_USER_OPCODE_RNG]"
        },
        {
          "direction": "out",
          "name": "user_operand_0",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "user_operand_1",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[`LM32_BYTE_SELECT_RNG]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[`LM32_CTYPE_RNG]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[`LM32_BTYPE_RNG]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[`LM32_WORD_RNG]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[`LM32_BYTE_SELECT_RNG]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[`LM32_CTYPE_RNG]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[`LM32_BTYPE_RNG]"
        }
      ],
      "lm32_top_full": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
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          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
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        {
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          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
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          "width": "[ (5-1):0]"
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        {
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          "name": "immediate",
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          "width": "[ (32-1):0]"
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          "name": "store",
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          "width": ""
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        {
          "direction": "out",
          "name": "size",
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          "width": "[ 1:0]"
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        {
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          "name": "sign_extend",
          "type": "wire",
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        {
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          "name": "adder_op",
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          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
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          "width": "[ 3:0]"
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        {
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          "name": "divide",
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          "name": "modulus",
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        {
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          "name": "branch",
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          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
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        {
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          "name": "scall",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
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          "width": ""
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "in",
          "name": "read_enable_f",
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          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
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          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
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          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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          "direction": "in",
          "name": "branch_predict_address_d",
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_x",
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
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          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
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          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "name": "pc_w",
          "type": "wire",
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        {
          "direction": "out",
          "name": "icache_stall_request",
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          "width": ""
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        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
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        {
          "direction": "in",
          "name": "jtag_address",
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          "width": "[ (32-1):0]"
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        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_full_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_medium": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
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          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_medium_debug": [
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          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "iram_i_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
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          "width": "[31:0]"
        },
        {
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          "name": "iram_i_dat_i",
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        {
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        {
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          "name": "iram_d_en_o",
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        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
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          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
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          "width": ""
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      ],
      "lm32_top_medium_icache": [
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          "name": "clk_i",
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        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
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        {
          "direction": "in",
          "name": "interrupt",
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        },
        {
          "direction": "in",
          "name": "I_DAT_I",
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        },
        {
          "direction": "in",
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        {
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          "name": "I_ERR_I",
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        {
          "direction": "in",
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          "name": "D_DAT_I",
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        {
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        {
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        {
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        {
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "I_SEL_O",
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          "width": "[ (4-1):0]"
        },
        {
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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        },
        {
          "direction": "out",
          "name": "I_BTE_O",
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        {
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        {
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        },
        {
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        },
        {
          "direction": "out",
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        },
        {
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        {
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        {
          "direction": "out",
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        },
        {
          "direction": "out",
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          "width": "[ (2-1):0]"
        },
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          "name": "value",
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          "direction": "in",
          "name": "kill_x",
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          "width": ""
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        {
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          "name": "divide_d",
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        {
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          "name": "operand_0_d",
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        {
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        {
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          "name": "result_x",
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        },
        {
          "direction": "out",
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        {
          "direction": "out",
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          "width": ""
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        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
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        {
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          "name": "stall_x",
          "type": "wire",
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        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
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          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
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          "name": "load_store_address_w",
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        {
          "direction": "in",
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        {
          "direction": "in",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_medium_icache_debug": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
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        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
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          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
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        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
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        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "divide",
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          "width": ""
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        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
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        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
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        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
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          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_minimal": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "lm32_top_wr_node": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "interrupt",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "I_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_DAT_I",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "D_ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "D_RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "I_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "I_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "I_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "D_DAT_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_ADR_O",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "D_CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_SEL_O",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "D_STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_CTI_O",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "D_LOCK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "D_BTE_O",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "value",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "stall_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "divide_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "modulus_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "operand_0_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "operand_1_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "result_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "divide_by_zero_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_a",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_operand_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "load_store_address_w",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "load_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "load_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "store_q_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sign_extend_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "size_x",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "in",
          "name": "dflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "d_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dcache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "load_data_w",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "stall_wb_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "d_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "d_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "d_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "in",
          "name": "instruction",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_0",
          "type": "wire",
          "width": "[ 0:0]"
        },
        {
          "direction": "out",
          "name": "d_result_sel_1",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "x_result_sel_csr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_mc_arith",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_sext",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_logic",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_add",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_compare",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_result_sel_mul",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "m_bypass_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_enable_0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_0",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "read_enable_1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "read_idx_1",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_idx",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "immediate",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "branch_offset",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "load",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "store",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[ 1:0]"
        },
        {
          "direction": "out",
          "name": "sign_extend",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adder_op",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "logic_op",
          "type": "wire",
          "width": "[ 3:0]"
        },
        {
          "direction": "out",
          "name": "direction",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "divide",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "modulus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "branch_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "bi_conditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bi_unconditional",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scall",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_taken_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_a",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "address_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "read_enable_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "refill_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "iflush",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "refill_address",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "inst",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_x",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "address_m",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "store_byte_select",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "load_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "valid_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "kill_f",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_predict_address_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "branch_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_mispredict_taken_m",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_target_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "in",
          "name": "i_dat_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "i_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_err_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_rty_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pc_f",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_d",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_x",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_m",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "pc_w",
          "type": "wire",
          "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "icache_stall_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_restart_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refill_request",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "icache_refilling",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_dat_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_adr_o",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "i_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_sel_o",
          "type": "wire",
          "width": "[ (4-1):0]"
        },
        {
          "direction": "out",
          "name": "i_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_cti_o",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "i_lock_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "i_bte_o",
          "type": "wire",
          "width": "[ (2-1):0]"
        },
        {
          "direction": "out",
          "name": "bus_error_d",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "instruction_f",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "instruction_d",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr",
          "type": "wire",
          "width": "[ (4 -1):0]"
        },
        {
          "direction": "in",
          "name": "csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "interrupt_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_update",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_reg_q",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_reg_addr_q",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_d",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_reg_addr_d",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "break_opcode",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_write_enable_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "csr_x",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_csr_write_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "jtag_csr",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "in",
          "name": "bret_q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_ss",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dc_re",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wp_match",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_read_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jtag_write_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "in",
          "name": "jtag_address",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_read_data",
          "type": "wire",
          "width": "[ 7:0]"
        },
        {
          "direction": "out",
          "name": "jtag_access_complete",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "exception_q_w",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jrx_csr_read_data",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "out",
          "name": "jtag_break",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jtag_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "non_debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "debug_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x_result_sel_shift",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_pc",
          "type": "wire",
          "width": "[ ((32-2)+2-1):2]"
        },
        {
          "direction": "out",
          "name": "trace_pc_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_exception",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_eid",
          "type": "wire",
          "width": "[ (3-1):0]"
        },
        {
          "direction": "out",
          "name": "trace_eret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "trace_bret",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_i_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "iram_d_en_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_csr_write_data_i",
          "type": "wire",
          "width": "[ (32-1):0]"
        },
        {
          "direction": "in",
          "name": "dbg_csr_addr_i",
          "type": "wire",
          "width": "[ (5-1):0]"
        },
        {
          "direction": "out",
          "name": "dbg_exception_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_break_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_d_adr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "iram_d_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "iram_stall_request_x",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iram_i_en_o",
          "type": "wire",
          "width": ""
        }
      ],
      "mpsoc_int_gen": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_awaddr",
          "type": "std_logic_vector",
          "width": "48 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awburst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awcache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awid",
          "type": "std_logic_vector",
          "width": "5 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awlen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awlock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_awprot",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AXI_awready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_awsize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_awuser",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_awvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_wdata",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_wlast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AXI_wready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AXI_wstrb",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_wvalid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AXI_bid",
          "type": "std_logic_vector",
          "width": "5 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AXI_bready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AXI_bresp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AXI_bvalid",
          "type": "std_logic",
          "width": ""
        }
      ],
      "pcie_wb": [
        {
          "direction": "in",
          "name": "clk125_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cal_clk50_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pcie_refclk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pcie_rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pcie_rx_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "pcie_tx_o",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "master_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "secded_ecc": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_i",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bwe_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "re_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "done_r_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "done_w_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "a_ram_o",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "d_ram_i",
          "type": "std_logic_vector",
          "width": "38 downto 0"
        },
        {
          "direction": "out",
          "name": "q_ram_o",
          "type": "std_logic_vector",
          "width": "38 downto 0"
        },
        {
          "direction": "out",
          "name": "we_ram_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "re_ram_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "valid_ram_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "lock_req_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "lock_grant_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "single_error_p_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "double_error_p_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "spi_top": [
        {
          "direction": "out",
          "name": "int_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "wire",
          "width": "[32-1:0]"
        },
        {
          "direction": "in",
          "name": "output",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ss_pad_o",
          "type": "wire",
          "width": "[SPI_SS_NB-1:0]"
        },
        {
          "direction": "out",
          "name": "sclk_pad_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mosi_pad_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "miso_pad_i",
          "type": "wire",
          "width": ""
        }
      ],
      "uart_wb_slave": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_addr_i",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_data_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_data_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_sel_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_sr_tx_busy_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_sr_rx_rdy_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "uart_bcr_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "uart_tdr_tx_data_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "uart_tdr_tx_data_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "uart_tdr_tx_data_load_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "uart_rdr_rx_data_i",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "rdr_rack_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "v6_hwfifo_wraper": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_wr_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_almost_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_almost_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wr_count_o",
          "type": "std_logic_vector",
          "width": "f_log2_size(g_size)-1 downto 0"
        }
      ],
      "voter_vec_status": [
        {
          "direction": "in",
          "name": "a",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "c",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "res",
          "type": "std_logic_vector",
          "width": "g_WIDTH - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "err",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wb16_to_wb32": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb16_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb16_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb32_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb32_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "wb_axi4lite_bridge": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ARVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "AWVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "BREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "WLAST",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "WVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ARADDR",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "AWADDR",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "WDATA",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "WSTRB",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "ARREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "AWREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RLAST",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RVALID",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WREADY",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BRESP",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "RRESP",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "RDATA",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_adr",
          "type": "std_logic_vector",
          "width": "c_wishbone_address_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_m2s",
          "type": "std_logic_vector",
          "width": "c_wishbone_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_sel",
          "type": "std_logic_vector",
          "width": "c_wishbone_data_width/8-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_cyc",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_stb",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_we",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_dat_s2m",
          "type": "std_logic_vector",
          "width": "c_wishbone_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_err",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_rty",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stall",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wb_conmax_top": [
        {
          "direction": "in",
          "name": "wb_masters_i",
          "type": "t_conmax_masters_i",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_masters_o",
          "type": "t_conmax_masters_o",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_slaves_i",
          "type": "t_conmax_slaves_i",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_slaves_o",
          "type": "t_conmax_slaves_o",
          "width": ""
        }
      ],
      "wb_i2c_bridge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scl_en_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sda_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sda_en_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i2c_addr_i",
          "type": "std_logic_vector",
          "width": "6 downto 0"
        },
        {
          "direction": "out",
          "name": "tip_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "err_p_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wdto_p_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wbm_stb_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wbm_cyc_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wbm_sel_o",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "wbm_we_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wbm_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wbm_dat_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wbm_adr_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wbm_ack_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wbm_rty_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wbm_err_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wb_irq_lm32": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dwb_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dwb_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "iwb_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "iwb_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq_slave_o",
          "type": "t_wishbone_slave_out_array",
          "width": "g_msi_queues-1 downto 0"
        },
        {
          "direction": "in",
          "name": "irq_slave_i",
          "type": "t_wishbone_slave_in_array",
          "width": "g_msi_queues-1 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        }
      ],
      "wb_irq_master": [
        {
          "direction": "out",
          "name": "irq_master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ctrl_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        }
      ],
      "wb_irq_timer": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_sys_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tm_tai8ns_i",
          "type": "std_logic_vector",
          "width": "63 downto 0"
        },
        {
          "direction": "out",
          "name": "ctrl_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ctrl_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "irq_master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        }
      ],
      "wb_serial_lcd": [
        {
          "direction": "in",
          "name": "slave_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_rstn_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "di_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "di_scp_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "di_lp_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "di_flm_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "di_dat_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wb_skidpad2": [
        {
          "direction": "in",
          "name": "stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "adr_i",
          "type": "std_logic_vector",
          "width": "g_adrbits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "dat_i",
          "type": "std_logic_vector",
          "width": "g_datbits-1 downto 0"
        },
        {
          "direction": "in",
          "name": "sel_i",
          "type": "std_logic_vector",
          "width": "(g_datbits/8)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stall_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "stb_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "adr_o",
          "type": "std_logic_vector",
          "width": "g_adrbits-1 downto 0"
        },
        {
          "direction": "out",
          "name": "dat_o",
          "type": "std_logic_vector",
          "width": "g_datbits-1 downto 0"
        },
        {
          "direction": "out",
          "name": "sel_o",
          "type": "std_logic_vector",
          "width": "(g_datbits/8)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "we_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stall_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wbgen2_dpssram": [
        {
          "direction": "in",
          "name": "clk_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_b_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr_a_i",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "addr_b_i",
          "type": "std_logic_vector",
          "width": "g_addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "data_a_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "data_b_i",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "data_a_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "data_b_o",
          "type": "std_logic_vector",
          "width": "g_data_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "bwsel_a_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "bwsel_b_i",
          "type": "std_logic_vector",
          "width": "(g_data_width+7)/8-1 downto 0"
        },
        {
          "direction": "in",
          "name": "rd_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rd_b_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_a_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_b_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wbgen2_eic": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wbgen2_fifo_async": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rd_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rd_req_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_data_o",
          "type": "std_logic_vector",
          "width": "g_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "rd_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "rd_usedw_o",
          "type": "std_logic_vector",
          "width": "g_usedw_size -1 downto 0"
        },
        {
          "direction": "in",
          "name": "wr_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_req_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wr_data_i",
          "type": "std_logic_vector",
          "width": "g_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wr_empty_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_full_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wr_usedw_o",
          "type": "std_logic_vector",
          "width": "g_usedw_size -1 downto 0"
        }
      ],
      "xaxi4lite_wb_bridge": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "axi4_master_o",
          "type": "t_axi4_lite_master_out_32",
          "width": ""
        },
        {
          "direction": "in",
          "name": "axi4_master_i",
          "type": "t_axi4_lite_master_in_32",
          "width": ""
        }
      ],
      "xwb_async_bridge": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_cs_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_wr_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_rd_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_bs_n_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "cpu_addr_i",
          "type": "std_logic_vector",
          "width": "g_cpu_address_width-1 downto 0"
        },
        {
          "direction": "inout",
          "name": "cpu_data_b",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "cpu_nwait_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        }
      ],
      "xwb_bus_fanout": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in_array",
          "width": "0 to g_num_outputs-1"
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out_array",
          "width": "0 to g_num_outputs-1"
        }
      ],
      "xwb_clock_monitor": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_in_i",
          "type": "std_logic_vector",
          "width": "g_num_clocks-1 downto 0"
        },
        {
          "direction": "in",
          "name": "pps_p1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_conmax": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in_array",
          "width": "0 to g_num_slaves-1"
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out_array",
          "width": "0 to g_num_slaves-1"
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in_array",
          "width": "0 to g_num_masters-1"
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out_array",
          "width": "0 to g_num_masters-1"
        }
      ],
      "xwb_dpram": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave1_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave1_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave2_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave2_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_dpram_mixed": [
        {
          "direction": "in",
          "name": "clk_slave1_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_slave2_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave1_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave1_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave2_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave2_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_ds182x_readout": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pps_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "onewire_b",
          "type": "std_logic",
          "width": ""
        }
      ],
      "xwb_fine_pulse_gen": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_ref_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_sys_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_ser_ext_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ext_trigger_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pps_p_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pulse_o",
          "type": "std_logic_vector",
          "width": "g_num_channels-1 downto 0"
        },
        {
          "direction": "out",
          "name": "clk_par_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_gpio_port": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "gpio_b",
          "type": "std_logic_vector",
          "width": "g_num_pins-1 downto 0"
        },
        {
          "direction": "out",
          "name": "gpio_out_o",
          "type": "std_logic_vector",
          "width": "g_num_pins-1 downto 0"
        },
        {
          "direction": "in",
          "name": "gpio_in_i",
          "type": "std_logic_vector",
          "width": "g_num_pins-1 downto 0"
        },
        {
          "direction": "out",
          "name": "gpio_oen_o",
          "type": "std_logic_vector",
          "width": "g_num_pins-1 downto 0"
        }
      ],
      "xwb_i2c_master": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        },
        {
          "direction": "out",
          "name": "int_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scl_pad_i",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        },
        {
          "direction": "out",
          "name": "scl_pad_o",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        },
        {
          "direction": "out",
          "name": "scl_padoen_o",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        },
        {
          "direction": "in",
          "name": "sda_pad_i",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        },
        {
          "direction": "out",
          "name": "sda_pad_o",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        },
        {
          "direction": "out",
          "name": "sda_padoen_o",
          "type": "std_logic_vector",
          "width": "g_num_interfaces-1 downto 0"
        }
      ],
      "xwb_indirect": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_wb_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_wb_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "xwb_lm32_mcs": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irq_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "host_wb_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "host_wb_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dbg_txd_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dbg_rxd_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dwb_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dwb_i",
          "type": "t_wishbone_master_in",
          "width": ""
        }
      ],
      "xwb_metadata": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_onewire_master": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        },
        {
          "direction": "out",
          "name": "int_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "owr_pwren_o",
          "type": "std_logic_vector",
          "width": "g_num_ports -1 downto 0"
        },
        {
          "direction": "out",
          "name": "owr_en_o",
          "type": "std_logic_vector",
          "width": "g_num_ports -1 downto 0"
        },
        {
          "direction": "in",
          "name": "owr_i",
          "type": "std_logic_vector",
          "width": "g_num_ports -1 downto 0"
        }
      ],
      "xwb_register": [
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "xwb_register_link": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "xwb_remapper": [
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "xwb_sdb_crossbar": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in_array",
          "width": "g_num_masters-1 downto 0"
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out_array",
          "width": "g_num_masters-1 downto 0"
        },
        {
          "direction": "in",
          "name": "msi_master_i",
          "type": "t_wishbone_master_in_array",
          "width": "g_num_masters-1 downto 0"
        },
        {
          "direction": "out",
          "name": "msi_master_o",
          "type": "t_wishbone_master_out_array",
          "width": "g_num_masters-1 downto 0"
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in_array",
          "width": "g_num_slaves -1 downto 0"
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out_array",
          "width": "g_num_slaves -1 downto 0"
        },
        {
          "direction": "in",
          "name": "msi_slave_i",
          "type": "t_wishbone_slave_in_array",
          "width": "g_num_slaves -1 downto 0"
        },
        {
          "direction": "out",
          "name": "msi_slave_o",
          "type": "t_wishbone_slave_out_array",
          "width": "g_num_slaves -1 downto 0"
        }
      ],
      "xwb_simple_pwm": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pwm_o",
          "type": "std_logic_vector",
          "width": "g_num_channels-1 downto 0"
        }
      ],
      "xwb_spi": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        },
        {
          "direction": "out",
          "name": "int_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pad_cs_o",
          "type": "std_logic_vector",
          "width": "g_num_slaves-1 downto 0"
        },
        {
          "direction": "out",
          "name": "pad_sclk_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "pad_mosi_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pad_miso_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "xwb_split": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "master_i",
          "type": "t_wishbone_master_in_array",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "master_o",
          "type": "t_wishbone_master_out_array",
          "width": "1 downto 0"
        }
      ],
      "xwb_streamer": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "r_master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "r_master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "w_master_i",
          "type": "t_wishbone_master_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "w_master_o",
          "type": "t_wishbone_master_out",
          "width": ""
        }
      ],
      "xwb_tics": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        }
      ],
      "xwb_vic": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "irqs_i",
          "type": "std_logic_vector",
          "width": "g_num_interrupts-1 downto 0"
        },
        {
          "direction": "out",
          "name": "irq_master_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "xwb_vuart": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "host_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "host_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "in",
          "name": "board_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "board_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        }
      ],
      "xwb_xc7_fw_update": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_cs_n_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_mosi_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "flash_miso_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "xwb_xil_multiboot": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wbs_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wbs_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_cs_n_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_sclk_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "spi_mosi_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "spi_miso_i",
          "type": "std_logic",
          "width": ""
        }
      ],
      "xwb_xilinx_fpga_loader": [
        {
          "direction": "in",
          "name": "clk_sys_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_n_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "slave_i",
          "type": "t_wishbone_slave_in",
          "width": ""
        },
        {
          "direction": "out",
          "name": "slave_o",
          "type": "t_wishbone_slave_out",
          "width": ""
        },
        {
          "direction": "out",
          "name": "desc_o",
          "type": "t_wishbone_device_descriptor",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xlx_cclk_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xlx_din_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xlx_program_b_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "xlx_init_b_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "xlx_done_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xlx_suspend_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "xlx_m_o",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "boot_trig_p1_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "boot_exit_p1_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "boot_en_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gpio_o",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        }
      ]
    },
    "top_modules": [
      "altera_async_fifo",
      "altera_sync_fifo",
      "axi4lite32_axi4full64_bridge",
      "axi4lite_axi4full_bridge",
      "axi4lite_i2c_master",
      "axi_gpio_expander",
      "cheby_dpssram",
      "dec_8b10b_ctrl",
      "dec_8b10b_disp",
      "dec_8b10b_lut",
      "flash_top",
      "gc_arbitrated_mux",
      "gc_argb_led_drv",
      "gc_async_counter_diff",
      "gc_async_signals_input_stage",
      "gc_bicolor_led_ctrl",
      "gc_cic",
      "gc_cic_combs",
      "gc_cic_decimator",
      "gc_cic_integrators",
      "gc_cic_ratio_change_detect",
      "gc_comparator",
      "gc_cordic",
      "gc_cordic_top",
      "gc_crc_gen",
      "gc_dec_8b10b",
      "gc_delay_gen",
      "gc_ds182x_interface",
      "gc_dual_pi_controller",
      "gc_dyn_extend_pulse",
      "gc_dyn_glitch_filt",
      "gc_enc_8b10b",
      "gc_freq_meas",
      "gc_frequency_meter",
      "gc_integer_divide",
      "gc_iq_demodulator",
      "gc_iq_demodulator_shifted",
      "gc_iq_modulator",
      "gc_moving_average",
      "gc_multichannel_frequency_meter",
      "gc_negedge",
      "gc_pi_regulator",
      "gc_pipelined_fir_filter",
      "gc_posedge",
      "gc_reset",
      "gc_reset_multi_aasd",
      "gc_rr_arbiter",
      "gc_scrambler_descrambler",
      "gc_serial_dac",
      "gc_sfp_i2c_adapter",
      "gc_single_reset_gen",
      "gc_soft_ramp_switch",
      "gc_sync_word_rd",
      "gc_word_packer",
      "generic_async_fifo_mixedw",
      "generic_dpram_dualclock",
      "generic_dpram_inst_7series",
      "generic_dpram_sameclock",
      "generic_shiftreg_fifo",
      "generic_spram",
      "lm32_cpu_full_debug",
      "lm32_cpu_medium",
      "lm32_cpu_medium_debug",
      "lm32_cpu_medium_icache",
      "lm32_cpu_medium_icache_debug",
      "lm32_cpu_minimal",
      "lm32_cpu_wr_node",
      "lm32_dcache_full",
      "lm32_dcache_full_debug",
      "lm32_debug_full_debug",
      "lm32_debug_medium_debug",
      "lm32_debug_medium_icache_debug",
      "lm32_debug_wr_node",
      "lm32_decoder_full",
      "lm32_decoder_full_debug",
      "lm32_decoder_medium",
      "lm32_decoder_medium_debug",
      "lm32_decoder_medium_icache",
      "lm32_decoder_medium_icache_debug",
      "lm32_decoder_minimal",
      "lm32_decoder_wr_node",
      "lm32_icache_full",
      "lm32_icache_full_debug",
      "lm32_icache_medium_debug",
      "lm32_icache_medium_icache",
      "lm32_icache_medium_icache_debug",
      "lm32_instruction_unit_full",
      "lm32_instruction_unit_full_debug",
      "lm32_instruction_unit_medium",
      "lm32_instruction_unit_medium_debug",
      "lm32_instruction_unit_medium_icache",
      "lm32_instruction_unit_medium_icache_debug",
      "lm32_instruction_unit_minimal",
      "lm32_instruction_unit_wr_node",
      "lm32_interrupt_full",
      "lm32_interrupt_full_debug",
      "lm32_interrupt_medium",
      "lm32_interrupt_medium_debug",
      "lm32_interrupt_medium_icache",
      "lm32_interrupt_medium_icache_debug",
      "lm32_interrupt_minimal",
      "lm32_interrupt_wr_node",
      "lm32_jtag_full_debug",
      "lm32_jtag_medium_debug",
      "lm32_jtag_medium_icache_debug",
      "lm32_load_store_unit_full",
      "lm32_load_store_unit_full_debug",
      "lm32_load_store_unit_medium",
      "lm32_load_store_unit_medium_debug",
      "lm32_load_store_unit_medium_icache",
      "lm32_load_store_unit_medium_icache_debug",
      "lm32_load_store_unit_minimal",
      "lm32_load_store_unit_wr_node",
      "lm32_mc_arithmetic_full",
      "lm32_mc_arithmetic_full_debug",
      "lm32_mc_arithmetic_medium",
      "lm32_mc_arithmetic_medium_debug",
      "lm32_mc_arithmetic_medium_icache",
      "lm32_mc_arithmetic_medium_icache_debug",
      "lm32_mc_arithmetic_minimal",
      "lm32_mc_arithmetic_wr_node",
      "lm32_top",
      "lm32_top_full",
      "lm32_top_full_debug",
      "lm32_top_medium",
      "lm32_top_medium_debug",
      "lm32_top_medium_icache",
      "lm32_top_medium_icache_debug",
      "lm32_top_minimal",
      "lm32_top_wr_node",
      "mpsoc_int_gen",
      "pcie_wb",
      "secded_ecc",
      "spi_top",
      "uart_wb_slave",
      "v6_hwfifo_wraper",
      "voter_vec_status",
      "wb16_to_wb32",
      "wb_axi4lite_bridge",
      "wb_conmax_top",
      "wb_i2c_bridge",
      "wb_irq_lm32",
      "wb_irq_master",
      "wb_irq_timer",
      "wb_serial_lcd",
      "wb_skidpad2",
      "wbgen2_dpssram",
      "wbgen2_eic",
      "wbgen2_fifo_async",
      "xaxi4lite_wb_bridge",
      "xwb_async_bridge",
      "xwb_bus_fanout",
      "xwb_clock_bridge",
      "xwb_clock_monitor",
      "xwb_conmax",
      "xwb_dpram",
      "xwb_dpram_mixed",
      "xwb_ds182x_readout",
      "xwb_fine_pulse_gen",
      "xwb_gpio_port",
      "xwb_i2c_master",
      "xwb_indirect",
      "xwb_lm32_mcs",
      "xwb_metadata",
      "xwb_onewire_master",
      "xwb_register",
      "xwb_register_link",
      "xwb_remapper",
      "xwb_sdb_crossbar",
      "xwb_simple_pwm",
      "xwb_spi",
      "xwb_split",
      "xwb_streamer",
      "xwb_tics",
      "xwb_vic",
      "xwb_vuart",
      "xwb_xc7_fw_update",
      "xwb_xil_multiboot",
      "xwb_xilinx_fpga_loader"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_axi_lite_slave",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements an AXI-Lite Slave Interface, which can be used to access registers and memory. On the user-side it provides a simple read/write/address/data interface.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "lightweight",
      "lite",
      "olo",
      "open",
      "slave"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_axi_pkg_protocol"
    ],
    "top_ports": {
      "olo_axi_lite_slave": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AxiLite_ArAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AxiLite_ArValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AxiLite_ArReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AxiLite_AwAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AxiLite_AwValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AxiLite_AwReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AxiLite_WData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AxiLite_WStrb",
          "type": "std_logic_vector",
          "width": "(AxiDataWidth_g/8) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AxiLite_WValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AxiLite_WReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AxiLite_BResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AxiLite_BValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AxiLite_BReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AxiLite_RData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AxiLite_RResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_AxiLite_RValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AxiLite_RReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rb_Addr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rb_Wr",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rb_ByteEna",
          "type": "std_logic_vector",
          "width": "(AxiDataWidth_g/8) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rb_WrData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rb_Rd",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rb_RdData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Rb_RdValid",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_axi_master_full",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a full AXI master. In contrast to olo_axi_master_simple, this entity can do unaligned transfers and it supports different width for the AXI interface than for the data interface.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "full",
      "master",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_axi_pkg_protocol"
    ],
    "top_ports": {
      "olo_axi_master_full": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdWr_Addr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdWr_Size",
          "type": "std_logic_vector",
          "width": "UserTransactionSizeBits_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdWr_LowLat",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdWr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CmdWr_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdRd_Addr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdRd_Size",
          "type": "std_logic_vector",
          "width": "UserTransactionSizeBits_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdRd_LowLat",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdRd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CmdRd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Wr_Data",
          "type": "std_logic_vector",
          "width": "UserDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Wr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Data",
          "type": "std_logic_vector",
          "width": "UserDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rd_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Done",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Error",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Done",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Error",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_AwAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_AwCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_AwReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_WData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_WStrb",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_WLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_WValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_WReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_BResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_BValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_BReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_ArAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_ArCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_ArReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_RData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_RResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_RLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_RValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_RReady",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_axi_master_simple",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple AXI master. Simple means: It does not support any unaligned reads/writes and it does not do any width conversions.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "master",
      "olo",
      "open",
      "simple"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_axi_pkg_protocol"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_axi_pl_stage",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements multiple pipeline stages for an axi4 interface.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "olo",
      "open",
      "pl"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_axi_pl_stage": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AwId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwAddr",
          "type": "std_logic_vector",
          "width": "AddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_AwReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AwLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_AwCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwQos",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_AwRegion",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "S_WData",
          "type": "std_logic_vector",
          "width": "DataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_WStrb",
          "type": "std_logic_vector",
          "width": "DataWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_WValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_WReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_WLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_WUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_BId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_BResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_BValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_BReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_BUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArAddr",
          "type": "std_logic_vector",
          "width": "AddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_ArReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_ArLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_ArCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArQos",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "S_ArRegion",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "S_RId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_RData",
          "type": "std_logic_vector",
          "width": "DataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_RValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "S_RReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_RResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "S_RLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "S_RUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwAddr",
          "type": "std_logic_vector",
          "width": "AddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_AwReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_AwLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_AwCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwQos",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_AwRegion",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_WData",
          "type": "std_logic_vector",
          "width": "DataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_WStrb",
          "type": "std_logic_vector",
          "width": "DataWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_WValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_WReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_WLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_WUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_BId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_BResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_BValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_BReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_BUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArAddr",
          "type": "std_logic_vector",
          "width": "AddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_ArReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_ArLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_ArCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArQos",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_ArRegion",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "M_RId",
          "type": "std_logic_vector",
          "width": "IdWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_RData",
          "type": "std_logic_vector",
          "width": "DataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_RValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_RReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_RResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_RLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_RUser",
          "type": "std_logic_vector",
          "width": "UserWidth_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Open Logic shared base packages (olo_base_pkg_math/logic/array/string/attribute) \u2014 extracted by RTL-P3.738 so consumers depend on them once via package_deps.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "amba",
      "axi",
      "bus",
      "full",
      "master",
      "olo",
      "open"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-06-19T18:06:40Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_base_pkg_array",
      "olo_base_pkg_attribute",
      "olo_base_pkg_logic",
      "olo_base_pkg_math",
      "olo_base_pkg_string"
    ],
    "top_ports": {
      "olo_axi_master_full": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdWr_Addr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdWr_Size",
          "type": "std_logic_vector",
          "width": "UserTransactionSizeBits_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdWr_LowLat",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdWr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CmdWr_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdRd_Addr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdRd_Size",
          "type": "std_logic_vector",
          "width": "UserTransactionSizeBits_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "CmdRd_LowLat",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CmdRd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CmdRd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Wr_Data",
          "type": "std_logic_vector",
          "width": "UserDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Wr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Data",
          "type": "std_logic_vector",
          "width": "UserDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rd_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Done",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Error",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Done",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Error",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_AwAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_AwCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_AwValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_AwReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_WData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_WStrb",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_WLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_WValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_WReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_BResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_BValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_BReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_ArAddr",
          "type": "std_logic_vector",
          "width": "AxiAddrWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArLen",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArSize",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArBurst",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArLock",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_ArCache",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArProt",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "M_Axi_ArValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_ArReady",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_RData",
          "type": "std_logic_vector",
          "width": "AxiDataWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_RResp",
          "type": "std_logic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "in",
          "name": "M_Axi_RLast",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "M_Axi_RValid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "M_Axi_RReady",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_arb_prio",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements an efficient priority arbiter. The highest index of the input has priority.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "arb",
      "arbiter",
      "arbitration",
      "olo",
      "open",
      "prio"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_arb_rr",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements an efficient round-robin arbiter.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "arb",
      "arbiter",
      "arbitration",
      "olo",
      "open",
      "rr"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_arb_wrr",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements an efficient weighted round-robin arbiter.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "arb",
      "arbiter",
      "arbitration",
      "olo",
      "open",
      "wrr"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_arb_wrr": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Weights",
          "type": "std_logic_vector",
          "width": "WeightWidth_g*GrantWidth_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Req",
          "type": "std_logic_vector",
          "width": "GrantWidth_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Grant",
          "type": "std_logic_vector",
          "width": "GrantWidth_g-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cam",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This components implements a content addressable memory.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "addressable",
      "cam",
      "content",
      "memory",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_cam": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rd_Content",
          "type": "std_logic_vector",
          "width": "ContentWidth_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Wr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Wr_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Wr_Content",
          "type": "std_logic_vector",
          "width": "ContentWidth_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Wr_Addr",
          "type": "std_logic_vector",
          "width": "log2ceil(Addresses_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Wr_Write",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Wr_Clear",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Wr_ClearAll",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Match_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Match_Match",
          "type": "std_logic_vector",
          "width": "Addresses_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Addr_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Addr_Found",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Addr_Addr",
          "type": "std_logic_vector",
          "width": "log2ceil(Addresses_g)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_bits",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Synchronizes parallel data bits across independent clock domains using configurable synchronization stages.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "bits",
      "cc",
      "clock",
      "crossing",
      "olo",
      "open"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_handshake",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic clock crossing that allows passing of data with the commonly used Valid/Ready handshake. The clock crossing is not meant to achieve high-performance but to be simple and safe.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "handshake",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_cc_handshake": [
        {
          "direction": "in",
          "name": "In_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_n2xn",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a clock crossing between two synchronous clocks where the input clock period is an integer multiple of the output clock period (output clock frequency is an integer multiple of the input clock frequency).",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "n2xn",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_cc_n2xn": [
        {
          "direction": "in",
          "name": "In_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_pulse",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic clock crossing that allows passing pulses from one clock domain to another. The pulse frequency must be significantly lower than then slower clock speed.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "olo",
      "open",
      "pulse"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_reset",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic clock crossing that allows to clock-cross resets. It does assert reset on the other clock domain immediately and de-asserts the reset synchronously to the corresponding clock.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "olo",
      "open",
      "reset"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_simple",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic clock crossing that allows passing single samples of data from one clock domain to another. It only works if sample rates are significantly lower than the clock speed of both domains.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "olo",
      "open",
      "simple"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_status",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Synchronizes status signals and reset signals across two independent clock domains with configurable synchronization stages.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "olo",
      "open",
      "status"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "preserved",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_cc_status": [
        {
          "direction": "in",
          "name": "In_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_cc_xn2n",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a clock crossing between two synchronous clocks where the output clock period is an integer multiple of the input clock period (input clock frequency is an integer multiple of the output clock frequency).",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cc",
      "clock",
      "crossing",
      "olo",
      "open",
      "xn2n"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_cc_xn2n": [
        {
          "direction": "in",
          "name": "In_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_RstIn",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_crc",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Description: A CRC generator based on a linear-feedback shifter register. Can be used to generate CRCs to add on TX side or to calculate CRCs to compare to received CRC on RX side.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "check",
      "crc",
      "cyclic",
      "olo",
      "open",
      "redundancy"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_crc_append",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Description: Append a CRC to AXI4-Stream packets.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "append",
      "check",
      "crc",
      "cyclic",
      "olo",
      "open",
      "redundancy"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_crc_append": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "DataWidth_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "DataWidth_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_crc_check",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Description: Check the CRC appended to AXI4-Stream packets and drop packets with errors.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "check",
      "crc",
      "cyclic",
      "olo",
      "open",
      "redundancy"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_crc_check": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "DataWidth_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "DataWidth_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_CrcErr",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_decode_firstbit",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a pipelined first bit decoder. It finds out which is the lowest index of a bit set in the input vecotr.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "decode",
      "firstbit",
      "olo",
      "open"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_delay",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a delay element. It is either emplemented in BRAM or SRL. The output is always a fabric register for improved timing.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "delay",
      "olo",
      "open"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_delay_cfg",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a delay element. It is either implemented in BRAM & SRL. The output is always a fabric register for improved timing. The delay is settable by a input and not fixed as the olo_base_delay.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cfg",
      "delay",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_delay_cfg": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Delay",
          "type": "std_logic_vector",
          "width": "log2ceil(MaxDelay_g+1)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "(Width_g - 1) downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_dyn_sft",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a dynamic shift implemented in multiple stages in order to achieve good timing.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "dyn",
      "olo",
      "open",
      "sft",
      "shift",
      "shifter"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_fifo_async",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic asynchronous FIFO. The clocks can be fully asynchronous (unrelated). It  has optional level- and almost-full/empty ports.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "async",
      "asynchronous",
      "buffer",
      "fifo",
      "olo",
      "open",
      "queue"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_fifo_async": [
        {
          "direction": "in",
          "name": "In_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Full",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Empty",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_AlmFull",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_AlmEmpty",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Level",
          "type": "std_logic_vector",
          "width": "log2ceil(Depth_g+1)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Full",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Empty",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_AlmFull",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_AlmEmpty",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Level",
          "type": "std_logic_vector",
          "width": "log2ceil(Depth_g+1)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_fifo_packet",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a synchronous packet FIFO. In contrast to a normal FIFO, it allows",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "buffer",
      "fifo",
      "olo",
      "open",
      "packet",
      "queue"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_fifo_sync",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic synchronous FIFO. It  has optional level- and almost-full/empty ports.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "buffer",
      "fifo",
      "olo",
      "open",
      "queue",
      "sync",
      "synchronizer",
      "synchronous"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_flowctrl_handler",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Implements full flow-control handling (including Ready/backpressure) for processing entities that do not support flow-control natively.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "flowctrl",
      "handler",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_flowctrl_handler": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "InWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "OutWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ToProc_Data",
          "type": "std_logic_vector",
          "width": "InWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "ToProc_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "FromProc_Data",
          "type": "std_logic_vector",
          "width": "OutWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "FromProc_Valid",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_latency_comp",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This module implements a latency compensation for signals that bypass some processing logic.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "comp",
      "latency",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_latency_comp": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Err_Overrun",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Err_Underrun",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_pl_stage",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a pipelinestage with handshaking (AXI-S Ready/Valild). The pipeline stage ensures all signals are registered in both directions (including Ready).",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "olo",
      "open",
      "pl"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_prbs",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "Description: A generic pseudo random binary sequence based on a linear-feedback shifter register.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "olo",
      "open",
      "prbs"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_prbs": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "BitsPerSymbol_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "State_Current",
          "type": "std_logic_vector",
          "width": "Polynomial_g'length-1 downto 0"
        },
        {
          "direction": "in",
          "name": "State_New",
          "type": "std_logic_vector",
          "width": "Polynomial_g'length-1 downto 0"
        },
        {
          "direction": "in",
          "name": "State_Set",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_ram_sdp",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a pure VHDL and vendor indpendent simple dual port RAM with optional byte enables.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "access",
      "memory",
      "olo",
      "open",
      "ram",
      "random",
      "sdp"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_ram_sp",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a pure VHDL and vendor indpendent true single-port RAM with optional byte-enables.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "access",
      "memory",
      "olo",
      "open",
      "ram",
      "random",
      "sp"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_ram_sp": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Addr",
          "type": "std_logic_vector",
          "width": "log2ceil(Depth_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Be",
          "type": "std_logic_vector",
          "width": "Width_g / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "WrEna",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "WrData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "RdData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_ram_tdp",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a pure VHDL and vendor indpendent true dual port RAM with optional byte enables.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008-relaxed",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "access",
      "memory",
      "olo",
      "open",
      "ram",
      "random",
      "tdp"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_ram_tdp": [
        {
          "direction": "in",
          "name": "A_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "A_Addr",
          "type": "std_logic_vector",
          "width": "log2ceil(Depth_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "A_Be",
          "type": "std_logic_vector",
          "width": "Width_g / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "A_WrEna",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "A_WrData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "A_RdData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "B_Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "B_Addr",
          "type": "std_logic_vector",
          "width": "log2ceil(Depth_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "B_Be",
          "type": "std_logic_vector",
          "width": "Width_g / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "B_WrEna",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "B_WrData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "B_RdData",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_rate_limit",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This component limits the rate of AXI4-Stream style handshaked interfaces to a specified maximum data rate. It can be used to avoid overloading downstream components.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "limit",
      "olo",
      "open",
      "rate"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_rate_limit": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cfg_Period",
          "type": "std_logic_vector",
          "width": "log2ceil(Period_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Cfg_MaxSamples",
          "type": "std_logic_vector",
          "width": "log2ceil(MaxSamples_g)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_reset_gen",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a reset generator. It generates a pulse of the specified duration after FPGA configuration. The reset output is High-Active according to the Open-Logic definitions.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "gen",
      "olo",
      "open",
      "reset"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_reset_gen": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RstOut",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RstIn",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_strobe_div",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic strobe divider. It forwards only every Nth single cycle pulse to the output.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "div",
      "divider",
      "olo",
      "open",
      "strobe"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_strobe_div": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Ratio",
          "type": "std_logic_vector",
          "width": "log2ceil(MaxRatio_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_strobe_gen",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic strobe generator. It produces pulses with a duration of one clock cycle at a given frequency.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "gen",
      "olo",
      "open",
      "strobe"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_tdm_mux",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a very basic mux for Time Division Multiplxed data input",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "multiplexer",
      "mux",
      "olo",
      "open",
      "tdm"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_tdm_mux": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_ChSel",
          "type": "std_logic_vector",
          "width": "log2ceil(Channels_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "Width_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_wconv_n2m",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple data-width conversion between arbitrary input and output widths.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "converter",
      "n2m",
      "olo",
      "open",
      "wconv",
      "width"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_base_wconv_n2m": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "InWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Be",
          "type": "std_logic_vector",
          "width": "InWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Out_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "OutWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Be",
          "type": "std_logic_vector",
          "width": "OutWidth_g / 8 - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_wconv_n2xn",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple data-width conversion. The output width must be an integer multiple of the input width (Wo = n*Wi).",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "converter",
      "n2xn",
      "olo",
      "open",
      "wconv",
      "width"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_base_wconv_xn2n",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple data-width conversion. The input width must be an integer multiple of the output width (Wi = n*Wo)",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "converter",
      "olo",
      "open",
      "wconv",
      "width",
      "xn2n"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_abs",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_abs function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "abs",
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_abs": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_add",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_add function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "add",
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_add": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_B",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_addsub",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_addsub function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "addsub",
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_addsub": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_B",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Add",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_bin_div",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a binary division of two fixed-point numbers using a non-restoring division algorithm.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "bin",
      "div",
      "divider",
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_bin_div": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Num",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(NumFmt_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Denom",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(DenomFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Quot",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_cic_dec_par_tdm",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a CIC decimator. It supports one or multiple channels. On the input side the channels are received in parallel (allowing one sample per cycle for every channel).",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cic",
      "dec",
      "decoder",
      "fix",
      "olo",
      "open",
      "par",
      "tdm"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_cic_dec_par_tdm": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cfg_Ratio",
          "type": "std_logic_vector",
          "width": "log2ceil(Ratio_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "Cfg_Shift",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "Cfg_GainCorr",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromStringTolerant(GainCorrCoefFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InFmt_g)*Channels_g-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_cic_dec_tdm",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a CIC decimator. It supports one or multiple channels (time-division-multiplexed). The decimation ratio can either be configurable or fixed.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cic",
      "dec",
      "decoder",
      "fix",
      "olo",
      "open",
      "tdm"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_cic_dec_tdm": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cfg_Ratio",
          "type": "std_logic_vector",
          "width": "log2ceil(Ratio_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Cfg_Shift",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "Cfg_GainCorr",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromStringTolerant(GainCorrCoefFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Last",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Data",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Last",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_compare",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_compare function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "compare",
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_compare": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_B",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_cordic_rot",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a rotating CORDIC algorithm in either pipelined or serial mode.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cordic",
      "fix",
      "olo",
      "open",
      "rot"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_cordic_rot": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Mag",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InMagFmt_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Ang",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InAngFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_I",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Q",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_cordic_vect",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a vectoring CORDIC algorithm in either pipelined or serial mode.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "cordic",
      "fix",
      "olo",
      "open",
      "vect"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_cordic_vect": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "In_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_I",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InFmt_g)-1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_Q",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Mag",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutMagFmt_g)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Ang",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(OutAngFmt_g)-1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_from_real",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_from_real function as entity. it does NOT include pipeline stages because real numbers are only used for synthesis/simuation. They do not exist in the hardware.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open",
      "real"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_from_real": [
        {
          "direction": "out",
          "name": "Out_Value",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_limit",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_limit function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "limit",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_limit": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Data",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(InFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_LimLo",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(LimLoFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_LimHi",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(LimHiFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_mult",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_mult function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "mult",
      "olo",
      "open"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_neg",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_neg function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "neg",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_neg": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_resize",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_resize function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open",
      "resize"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_round",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_round function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open",
      "round"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_saturate",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_saturate function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open",
      "saturate"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_sub",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_sub function as entity. Includes pipeline stages and allows usage from Verilog.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_sub": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "In_B",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Out_Result",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_fix_to_real",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements the cl_fix_to_real function as entity. it does NOT include pipeline stages because real numbers are only used for synthesis/simuation. They do not exist in the hardware.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "fix",
      "olo",
      "open",
      "real"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_fix_pkg"
    ],
    "top_ports": {
      "olo_fix_to_real": [
        {
          "direction": "in",
          "name": "In_A",
          "type": "std_logic_vector",
          "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Out_Value",
          "type": "real",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_clk_meas",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity measures the frequency of a clock under the assumption that the frequency of the main-clock (Clk) is exactly correct.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "clk",
      "clock",
      "interface",
      "intf",
      "meas",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_intf_clk_meas": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ClkTest",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Freq_Hz",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "Freq_Valid",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_debounce",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a debouncer for button and switch inputs. It contains a double stage synchronizer to synchronize those inputs to the clock.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "debounce",
      "interface",
      "intf",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_intf_debounce": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "DataAsync",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "DataOut",
          "type": "std_logic_vector",
          "width": "Width_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_i2c_master",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple I2C-master (multi master capable)",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "circuit",
      "i2c",
      "inter-integrated",
      "interface",
      "intf",
      "master",
      "olo",
      "open"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "provides_packages": [
      "olo_intf_i2c_master_pkg"
    ],
    "top_ports": {
      "olo_intf_i2c_master": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Cmd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cmd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cmd_Command",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "in",
          "name": "Cmd_Data",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "Cmd_Ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cmd_ClkDiv",
          "type": "std_logic_vector",
          "width": "ClkDivBits_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Resp_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_Command",
          "type": "std_logic_vector",
          "width": "2 downto 0"
        },
        {
          "direction": "out",
          "name": "Resp_Data",
          "type": "std_logic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "Resp_Ack",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_ArbLost",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_SeqErr",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Status_BusBusy",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Status_CmdTo",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "I2c_Scl",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "I2c_Sda",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I2c_Scl_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I2c_Scl_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I2c_Scl_t",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "I2c_Sda_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I2c_Sda_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "I2c_Sda_t",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_spi_master",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple SPI-master",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "interface",
      "intf",
      "master",
      "olo",
      "open",
      "peripheral",
      "serial",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_intf_spi_master": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cmd_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Cmd_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Cmd_Slave",
          "type": "std_logic_vector",
          "width": "log2ceil(SlaveCnt_g) - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Cmd_Data",
          "type": "std_logic_vector",
          "width": "MaxTransWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Cmd_TransWidth",
          "type": "std_logic_vector",
          "width": "log2ceil(MaxTransWidth_g+1)-1 downto 0"
        },
        {
          "direction": "out",
          "name": "Resp_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_Data",
          "type": "std_logic_vector",
          "width": "MaxTransWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Spi_Sclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Spi_Mosi",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Spi_Miso",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Spi_Cs_n",
          "type": "std_logic_vector",
          "width": "SlaveCnt_g - 1 downto 0"
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_spi_slave",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple SPI-slave",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "interface",
      "intf",
      "olo",
      "open",
      "peripheral",
      "serial",
      "slave",
      "spi"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_intf_spi_slave": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rx_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rx_Data",
          "type": "std_logic_vector",
          "width": "TransWidth_g - 1 downto 0"
        },
        {
          "direction": "in",
          "name": "Tx_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Tx_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Tx_Data",
          "type": "std_logic_vector",
          "width": "TransWidth_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Resp_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_Sent",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_Aborted",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Resp_CleanEnd",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Spi_Sclk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Spi_Mosi",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Spi_Cs_n",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Spi_Miso",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Spi_Miso_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Spi_Miso_t",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_sync",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This is a simple double-stage synchronizer for synchronizing external signals to the internal system clock.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "interface",
      "intf",
      "olo",
      "open",
      "sync",
      "synchronizer",
      "synchronous"
    ],
    "role": "component",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ]
  },
  {
    "namespace": "open-logic",
    "name": "olo_intf_uart",
    "latest": "4.4.1",
    "versions": [
      "4.4.1"
    ],
    "description": "This entity implements a simple UART.",
    "license": "PSI-HDL-1.0",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "olo",
    "source_url": "https://github.com/open-logic/open-logic.git",
    "tags": [
      "asynchronous",
      "interface",
      "intf",
      "olo",
      "open",
      "receiver",
      "serial",
      "transmitter",
      "uart",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-04-15T23:18:14Z",
    "updated_at": "2026-03-10T06:51:30+01:00",
    "package_deps": [
      "open-logic/olo_base"
    ],
    "desc_source": "header",
    "external_uses": [
      {
        "library": "work",
        "package": "en_cl_fix_pkg"
      },
      {
        "library": "work",
        "package": "en_cl_fix_private_pkg"
      }
    ],
    "top_ports": {
      "olo_intf_uart": [
        {
          "direction": "in",
          "name": "Clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Rst",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Tx_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Tx_Ready",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Tx_Data",
          "type": "std_logic_vector",
          "width": "DataBits_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rx_Valid",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Rx_Data",
          "type": "std_logic_vector",
          "width": "DataBits_g - 1 downto 0"
        },
        {
          "direction": "out",
          "name": "Rx_ParityError",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Uart_Tx",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Uart_Rx",
          "type": "std_logic",
          "width": ""
        }
      ]
    }
  },
  {
    "namespace": "opencores",
    "name": "1000base-x",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "1000BASE-X physical coding sublayer (PCS) implementing IEEE 802.3 8b/10b encoding and synchronization for SFP-attached 1G optical transceivers.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/1000base-x.git",
    "tags": [
      "1000basex",
      "8b10b",
      "decoder",
      "encoder",
      "management",
      "output",
      "receive",
      "receiver",
      "synchronizer",
      "synchronous",
      "transmit",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T23:36:17Z",
    "updated_at": "2012-02-22T23:59:47+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "top_ports": {
      "ge_1000baseX_test": [
        {
          "direction": "in",
          "name": "reset_pin",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "GE_125MHz_ref_ckpin",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tbi_rx_ckpin",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "tbi_rxd",
          "type": "wire",
          "width": "[9:0]"
        },
        {
          "direction": "out",
          "name": "tbi_txd",
          "type": "wire",
          "width": "[9:0]"
        },
        {
          "direction": "out",
          "name": "gmii_rxd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "gmii_rx_dv",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_rx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_col",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "gmii_cs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_txd",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "gmii_tx_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gmii_tx_er",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "sync_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "loop_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prbs_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal_detect",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sync",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "inout",
          "name": "mdio",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mdio_ckpin",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "ge_1000baseX_test"
    ]
  },
  {
    "namespace": "opencores",
    "name": "6809_6309_compatible_core",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Motorola 6809 / Hitachi 6309 8/16-bit hybrid processor compatible with both ISAs, 16-bit address space, dual accumulator.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/6809_6309_compatible_core.git",
    "tags": [
      "alu",
      "calc",
      "cpu",
      "decode",
      "ea",
      "mc6809",
      "op",
      "processor"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T23:52:00Z",
    "updated_at": "2014-07-07T03:57:00+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "top_ports": {
      "MC6809_cpu": [
        {
          "direction": "in",
          "name": "cpu_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_nmi_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_irq_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cpu_firq_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cpu_state_o",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "out",
          "name": "cpu_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cpu_oe_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "cpu_addr_o",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "cpu_data_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "cpu_data_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "debug_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "debug_data_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mux",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "will",
          "type": "wire",
          "width": ""
        }
      ],
      "alu16": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "alu8": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
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          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "arith16": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "arith8": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "decode_ea": [
        {
          "direction": "in",
          "name": "cpu_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "opcode",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "postbyte0",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "page2_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "page3_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "path_left_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_left_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "write_dest",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "source_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "result_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mode",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "optype",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "use_s",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eapostbyte",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "noofs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_post",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "isind",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_opcode",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "dec_alu_right_path_mod",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "dest_flags",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "cond_taken",
          "type": "wire",
          "width": ""
        }
      ],
      "decode_op": [
        {
          "direction": "in",
          "name": "cpu_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "opcode",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "postbyte0",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "page2_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "page3_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "path_left_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_left_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "write_dest",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "source_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "result_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mode",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "optype",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "use_s",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eapostbyte",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "noofs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_post",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "isind",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_opcode",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "dec_alu_right_path_mod",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "dest_flags",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "cond_taken",
          "type": "wire",
          "width": ""
        }
      ],
      "decode_regs": [
        {
          "direction": "in",
          "name": "cpu_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "opcode",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "postbyte0",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "page2_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "page3_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "path_left_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_left_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "path_right_addr_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dest_reg_lo",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "write_dest",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "source_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "result_size",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mode",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "optype",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "use_s",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "eapostbyte",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "noofs",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs8",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ofs16",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "write_post",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "isind",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_opcode",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "dec_alu_right_path_mod",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "dest_flags",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "cond_taken",
          "type": "wire",
          "width": ""
        }
      ],
      "logic8": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "mul8x8": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "regblock": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "path_left_addr",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "path_right_addr",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "write_reg_addr",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "exg_dest_r",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "eapostbyte",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "offset16",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "write_reg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "write_post",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "write_pc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "write_tfr",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "write_exg",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "inc_pc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "inc_su",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dec_su",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "use_s",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_w",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "new_pc",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR_in",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "write_flags",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "set_e",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clear_e",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CCR_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "path_left_data",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "path_right_data",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "eamem_addr_o",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "reg_pc",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "reg_dp",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "reg_su",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "acca",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "accb",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "ix",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "iy",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "s",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "u",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "pc",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg_post_o",
          "type": "wire",
          "width": "[15:0]"
        }
      ],
      "shift8": [
        {
          "direction": "in",
          "name": "clk_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "a_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "b_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "CCR",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "opcode_in",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "sz_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "q_out",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "CCRo",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "carry_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "half_c_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "carry_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "overflow_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "half_c_out",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow_in",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "q_mul_in",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[15:0]"
        }
      ]
    },
    "top_modules": [
      "MC6809_cpu",
      "alu16",
      "alu8",
      "arith16",
      "arith8",
      "decode_ea",
      "decode_op",
      "decode_regs",
      "logic8",
      "mul8x8",
      "regblock",
      "shift8"
    ]
  },
  {
    "namespace": "opencores",
    "name": "8051",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Intel 8051 / 8052-compatible 8-bit microcontroller with peripheral ecosystem (UART, timers, I2C, SPI) and Wishbone host bus support.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/8051.git",
    "tags": [
      "access",
      "accumulator",
      "asynchronous",
      "decoder",
      "iinterface",
      "interface",
      "multiply",
      "receiver",
      "register",
      "transmitter",
      "universal",
      "wishbone"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T23:52:00Z",
    "updated_at": "2003-07-15T09:38:49+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "top_ports": {
      "oc8051_top": [
        {
          "direction": "in",
          "name": "wb_rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "int0_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wbd_dat_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "output",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wbd_dat_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "p0_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "p1_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "p2_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "p3_i",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "rxd_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "txd_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "t0_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "t1_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "t2_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "t2ex_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scanb_rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scanb_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scanb_si",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "scanb_so",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "scanb_en",
          "type": "wire",
          "width": ""
        }
      ],
      "rom0": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "o",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "rom1": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
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        },
        {
          "direction": "out",
          "name": "ea_int",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "o",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "rom10": [
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          "name": "rst",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
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        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
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        },
        {
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        {
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          "name": "rst",
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        },
        {
          "direction": "in",
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        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "o",
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        }
      ],
      "rom101": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "o",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "rom102": [
        {
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          "name": "rst",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "o",
          "type": "wire",
          "width": "[7:0]"
        }
      ],
      "rom103": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
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        },
        {
          "direction": "out",
          "name": "o",
          "type": "wire",
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        }
      ],
      "rom104": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
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        },
        {
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      ],
      "rom105": [
        {
          "direction": "in",
          "name": "rst",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "addr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "ea_int",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
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        },
        {
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      ],
      "rom106": [
        {
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        },
        {
          "direction": "in",
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          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
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          "width": "[31:0]"
        },
        {
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        },
        {
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          "name": "o",
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        }
      ],
      "rom107": [
        {
          "direction": "in",
          "name": "rst",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
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          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
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        },
        {
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        },
        {
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      ],
      "rom108": [
        {
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        },
        {
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        },
        {
          "direction": "out",
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        },
        {
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        {
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        {
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      ],
      "rom109": [
        {
          "direction": "in",
          "name": "rst",
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        },
        {
          "direction": "in",
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          "type": "wire",
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        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "data_o",
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          "width": "[31:0]"
        },
        {
          "direction": "in",
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        },
        {
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      ],
      "rom11": [
        {
          "direction": "in",
          "name": "rst",
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          "width": ""
        },
        {
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        {
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        },
        {
          "direction": "out",
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        },
        {
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        {
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      ],
      "rom110": [
        {
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          "name": "rst",
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        },
        {
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        {
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        },
        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "enable_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fault_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "break_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_addr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "mem_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "mem_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "mem_cti_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "mem_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "mem_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "mem_stall_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "mem_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "A",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "B",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ex_result_w",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "flops",
          "type": "wire",
          "width": ""
        }
      ],
      "cpu_if": [
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "imem0_addr_o",
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        },
        {
          "direction": "in",
          "name": "imem0_data_i",
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          "width": "[31:0]"
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        {
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        },
        {
          "direction": "out",
          "name": "imem0_stb_o",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "imem0_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "imem0_cti_o",
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        {
          "direction": "in",
          "name": "imem0_ack_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "imem0_stall_i",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem0_addr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "dmem0_data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "dmem0_data_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "dmem0_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dmem0_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem0_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem0_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem0_cti_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "dmem0_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dmem0_stall_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem1_addr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "dmem1_data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "dmem1_data_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "dmem1_sel_o",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "dmem1_we_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem1_stb_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem1_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem1_cti_o",
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          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "dmem1_ack_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dmem1_stall_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem2_addr_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "dmem2_data_o",
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        },
        {
          "direction": "in",
          "name": "dmem2_data_i",
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        {
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        },
        {
          "direction": "out",
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        },
        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem2_cyc_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dmem2_cti_o",
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        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "dmem2_stall_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fault_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "break_o",
          "type": "wire",
          "width": ""
        },
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          "direction": "in",
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          "width": ""
        },
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          "direction": "in",
          "name": "nmi_i",
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          "width": ""
        }
      ],
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          "name": "clk_i",
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        },
        {
          "direction": "in",
          "name": "rst_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "ext_intr_i",
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          "width": "[(EXTERNAL_INTERRUPTS - 1):0]"
        },
        {
          "direction": "out",
          "name": "intr_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "io_addr_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "io_data_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "io_data_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "io_we_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "io_stb_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "io_ack_o",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
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      "cpu_if",
      "soc"
    ]
  },
  {
    "namespace": "opencores",
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    "latest": "master",
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      "master"
    ],
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    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
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      "1024x128",
      "arbitration",
      "asynchronous",
      "controller",
      "converter",
      "coprocessor",
      "decompile",
      "interrupt",
      "multiply",
      "protocol",
      "transmitter",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T22:57:14Z",
    "updated_at": "2013-05-20T21:22:28+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
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          "direction": "in",
          "name": "i_sys_clk",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "i_ddr_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_cmd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_cmd_instr",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "i_cmd_byte_addr",
          "type": "wire",
          "width": "[ADDR_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "o_cmd_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_wr_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_wr_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_wr_mask",
          "type": "wire",
          "width": "[DATA_WIDTH/8-1:0]"
        },
        {
          "direction": "in",
          "name": "i_wr_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "i_wr_addr_32",
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          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "o_rd_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "o_rd_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_ddr_cmd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_ddr_cmd_instr",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "o_ddr_cmd_byte_addr",
          "type": "wire",
          "width": "[ADDR_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "i_ddr_cmd_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_ddr_wr_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_ddr_wr_en",
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        },
        {
          "direction": "out",
          "name": "o_ddr_wr_mask",
          "type": "wire",
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        {
          "direction": "out",
          "name": "o_ddr_wr_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "o_ddr_wr_addr_32",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "i_ddr_rd_data",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "i_ddr_rd_valid",
          "type": "wire",
          "width": ""
        }
      ],
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          "direction": "in",
          "name": "i_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_wb_adr",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "i_wb_sel",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "i_wb_we",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_wb_dat",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "i_wb_dat",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "i_wb_cyc",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_wb_stb",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_wb_ack",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_wb_err",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_cmd_en",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_cmd_instr",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "o_cmd_byte_addr",
          "type": "wire",
          "width": "[29:0]"
        },
        {
          "direction": "in",
          "name": "i_cmd_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_wr_full",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "o_wr_mask",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "o_wr_data",
          "type": "wire",
          "width": "[127:0]"
        },
        {
          "direction": "in",
          "name": "i_rd_data",
          "type": "wire",
          "width": "[127:0]"
        },
        {
          "direction": "in",
          "name": "i_rd_empty",
          "type": "wire",
          "width": ""
        }
      ],
      "xs6_sram_2048x32_byte_en": [
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          "direction": "in",
          "name": "i_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_write_data",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "i_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_address",
          "type": "wire",
          "width": "[10:0]"
        },
        {
          "direction": "in",
          "name": "i_byte_enable",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "o_read_data",
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        }
      ],
      "xs6_sram_256x32_byte_en": [
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          "direction": "in",
          "name": "i_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_write_data",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "i_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_address",
          "type": "wire",
          "width": "[ADDRESS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "i_byte_enable",
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          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "o_read_data",
          "type": "wire",
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        }
      ],
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_write_data",
          "type": "wire",
          "width": "[127:0]"
        },
        {
          "direction": "in",
          "name": "i_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "i_address",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "i_byte_enable",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "out",
          "name": "o_read_data",
          "type": "wire",
          "width": "[127:0]"
        }
      ]
    },
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      "wb_ddr3_bridge",
      "xs6_sram_2048x32_byte_en",
      "xs6_sram_256x32_byte_en",
      "xs6_sram_512x128_byte_en"
    ]
  },
  {
    "namespace": "opencores",
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    "latest": "master",
    "versions": [
      "master"
    ],
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    "license_class": "permissive",
    "language": "verilog",
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    "tags": [
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      "bus",
      "control",
      "memory",
      "microcode",
      "registers"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T23:52:00Z",
    "updated_at": "2011-02-24T20:04:55+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
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          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
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          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "ao68000": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
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        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
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        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
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        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "bus_control": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "condition": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "decoder": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "memory_registers": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "microcode_branch": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
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          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
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          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "in",
          "name": "An_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_write_enable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Dn_size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "micro_pc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "micro_data",
          "type": "wire",
          "width": "[87:0]"
        },
        {
          "direction": "in",
          "name": "the",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "decoder_micropc",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "save_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_write",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "perform_ea_read",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "out",
          "name": "load_ea",
          "type": "wire",
          "width": "[8:0]"
        },
        {
          "direction": "in",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "cond",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ccr",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "condition",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "alu_control",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "out",
          "name": "alu_signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alu_mult_div_ready",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "overflow",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid_32",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_address_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "jmp_bus_trap",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "finished",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "branch_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "branch_offset",
          "type": "wire",
          "width": "[3:0]"
        }
      ],
      "registers": [
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset_n",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "wire",
          "width": "[31:2]"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ERR_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "RTY_I",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SGL_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "BLK_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "RMW_O",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CTI_O",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "BTE_O",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "fc_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ipl_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "reset_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "blocked_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "signal",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "supervisor_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ipm_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_i",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "address_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "address_type_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_write_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "data_read_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_change_i",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_o",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_32_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "prefetch_ir_valid_80_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_address_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "jmp_bus_trap_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "finished_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "interrupt_trap_o",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "out",
          "name": "interrupt_mask_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "rw_state_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fc_state_o",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "fault_address_state_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "data_read",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir",
          "type": "wire",
          "width": "[79:0]"
        },
        {
          "direction": "in",
          "name": "prefetch_ir_valid",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "result",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "sr",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "rw_state",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "fc_state",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "fault_address_state",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "interrupt_mask",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "decoder_trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "usp",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "Dn_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_output",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "pc_change",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ea_reg",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_reg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "ea_mod",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "ea_mod_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "ea_type",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "ea_type_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand1",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand1_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "operand2",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "operand2_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "address",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "address_type",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "address_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "size",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "size_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "movem_modreg",
          "type": "wire",
          "width": "[5:0]"
        },
        {
          "direction": "in",
          "name": "movem_modreg_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "movem_loop",
          "type": "wire",
          "width": "[4:0]"
        },
        {
          "direction": "in",
          "name": "movem_loop_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "movem_reg",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "movem_reg_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "ir",
          "type": "wire",
          "width": "[15:0]"
        },
        {
          "direction": "in",
          "name": "ir_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "pc",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "pc_control",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "out",
          "name": "trap",
          "type": "wire",
          "width": "[7:0]"
        },
        {
          "direction": "in",
          "name": "trap_control",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "offset",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "offset_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "index",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "index_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "stop_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "stop_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "trace_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "trace_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "group_0_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "group_0_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "instruction_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "instruction_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "read_modify_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "read_modify_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_reset_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_reset_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_interrupt_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_interrupt_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_read_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_read_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_write_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_write_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "do_blocked_flag",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "do_blocked_flag_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "data_write",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "data_write_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_address",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "in",
          "name": "An_address_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "An_input",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "An_input_control",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "out",
          "name": "Dn_address",
          "type": "wire",
          "width": "[2:0]"
        },
        {
          "direction": "in",
          "name": "Dn_address_control",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "decoder_alu",
          "type": "wire",
          "width": "[17:0]"
        },
        {
          "direction": "out",
          "name": "decoder_alu_reg",
          "type": "wire",
          "width": "[17:0]"
        },
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "nextDout",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "xRes",
          "type": "wire",
          "width": "[X_RES_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "yRes",
          "type": "wire",
          "width": "[Y_RES_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "video",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "has",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "pixel",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "always",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "advanceRead",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "advanceWrite",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "writeData",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "writeAddress",
          "type": "wire",
          "width": "[ADDRESS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "writeEnable",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "fillCount",
          "type": "wire",
          "width": "[BUFFER_SIZE_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "readData0",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "readData1",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "out",
          "name": "readData2",
          "type": "wire",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "readAddress",
          "type": "wire",
          "width": "[ADDRESS_WIDTH-1:0]"
        },
        {
          "direction": "in",
          "name": "dataA",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        },
        {
          "direction": "in",
          "name": "addrA",
          "type": "wire",
          "width": "[(ADDRESS_WIDTH-1):0]"
        },
        {
          "direction": "in",
          "name": "weA",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "qA",
          "type": "wire",
          "width": "[(DATA_WIDTH-1):0]"
        }
      ]
    },
    "top_modules": [
      "bilinearDemosaic",
      "ramDualPort",
      "ramFifo"
    ]
  },
  {
    "namespace": "opencores",
    "name": "binary_to_bcd",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "BCD to binary converter, serial implementation, 1 clock per input bit. Description: See description below (which suffices for IP core specification document.)",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/binary_to_bcd.git",
    "tags": [
      "bcd",
      "binary"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-05T10:26:01Z",
    "updated_at": "2005-10-25T06:18:50+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-05",
    "desc_source": "header",
    "top_ports": {
      "bcd_to_binary": [
        {
          "direction": "in",
          "name": "bit",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "digit",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "digits",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "bits",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "number",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "will",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "register",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "values",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ce_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "start_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dat_bcd_i",
          "type": "wire",
          "width": "[4*BCD_DIGITS_IN_PP-1:0]"
        },
        {
          "direction": "in",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dat_binary_o",
          "type": "wire",
          "width": "[BITS_OUT_PP-1:0]"
        },
        {
          "direction": "out",
          "name": "done_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din",
          "type": "wire",
          "width": "[4*BCD_DIGITS_IN_PP-1:0]"
        },
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        }
      ],
      "binary_to_bcd": [
        {
          "direction": "in",
          "name": "bit",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "bits",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "digits",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "parameter",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ce_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "start_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "dat_binary_i",
          "type": "wire",
          "width": "[BITS_IN_PP-1:0]"
        },
        {
          "direction": "in",
          "name": "bus",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "dat_bcd_o",
          "type": "wire",
          "width": "[4*BCD_DIGITS_OUT_PP-1:0]"
        },
        {
          "direction": "out",
          "name": "done_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "din",
          "type": "wire",
          "width": "[4*BCD_DIGITS_OUT_PP-1:0]"
        },
        {
          "direction": "in",
          "name": "newbit",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "and",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "registers",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "bcd_to_binary",
      "binary_to_bcd"
    ]
  },
  {
    "namespace": "opencores",
    "name": "boundaries",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Clock-domain-boundary primitive library covering arbiter, basic FIFOs, clock detection, clock switching (2/3/4/8 sources), and debouncer for safe cross-domain glue.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/boundaries.git",
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      "basic",
      "buffer",
      "clock",
      "detect",
      "fifo",
      "queue",
      "random",
      "switch2",
      "switch3",
      "switch4",
      "switch8"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-05T07:09:59Z",
    "updated_at": "2004-07-07T12:41:55+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "top_ports": {
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          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reqst",
          "type": "wire",
          "width": "[RCNT-1:0]"
        },
        {
          "direction": "out",
          "name": "grant",
          "type": "wire",
          "width": "[RCNT-1:0]"
        }
      ],
      "bc_fifo_basic": [
        {
          "direction": "out",
          "name": "data",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "put_rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "get_rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "get_clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "get_do",
          "type": "wire",
          "width": "[DW-1:0]"
        },
        {
          "direction": "in",
          "name": "get",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "get_have",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "put_clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "put_di",
          "type": "wire",
          "width": "[DW-1:0]"
        },
        {
          "direction": "in",
          "name": "put",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "put_need",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[AW:0]"
        },
        {
          "direction": "in",
          "name": "g",
          "type": "wire",
          "width": "[AW:0]"
        }
      ],
      "clock_detect": [
        {
          "direction": "in",
          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "will",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "to",
          "type": "wire",
          "width": ""
        },
        {
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          "name": "is",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "rst_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sclk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "alive_o",
          "type": "wire",
          "width": ""
        }
      ],
      "clock_switch2_basic": [
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          "direction": "in",
          "name": "rst0_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk0_i",
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        },
        {
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        {
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        },
        {
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          "name": "enable",
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        {
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          "name": "select",
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        },
        {
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        },
        {
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          "width": ""
        },
        {
          "direction": "in",
          "name": "gclk0",
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          "width": ""
        }
      ],
      "clock_switch3_basic": [
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        },
        {
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        {
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        {
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        },
        {
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        },
        {
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        },
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          "name": "enable",
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          "width": ""
        },
        {
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          "name": "clock",
          "type": "wire",
          "width": ""
        },
        {
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        {
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        {
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          "name": "always",
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        },
        {
          "direction": "in",
          "name": "gclk0",
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        }
      ],
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        },
        {
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        },
        {
          "direction": "in",
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        },
        {
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          "name": "clk1_i",
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          "width": ""
        },
        {
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        },
        {
          "direction": "in",
          "name": "clk2_i",
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        },
        {
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        },
        {
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        },
        {
          "direction": "in",
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        },
        {
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          "name": "select",
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        },
        {
          "direction": "out",
          "name": "clk_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "always",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "gclk0",
          "type": "wire",
          "width": ""
        }
      ],
      "clock_switch8_basic": [
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk0_i",
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        },
        {
          "direction": "in",
          "name": "rst1_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "clk1_i",
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          "width": ""
        },
        {
          "direction": "in",
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          "width": ""
        },
        {
          "direction": "in",
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        },
        {
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          "name": "rst3_i",
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        },
        {
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          "width": ""
        },
        {
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        },
        {
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        },
        {
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        },
        {
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        },
        {
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          "name": "clk6_i",
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        },
        {
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          "name": "rst7_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "clk7_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "enable",
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        },
        {
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          "width": "[2:0]"
        },
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        },
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        {
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          "direction": "in",
          "name": "button_i",
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        {
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        },
        {
          "direction": "in",
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          "width": ""
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        {
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          "name": "to",
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        },
        {
          "direction": "out",
          "name": "default",
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        }
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        },
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        },
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        },
        {
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        },
        {
          "direction": "out",
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          "type": "wire",
          "width": "[DW-1:0]"
        },
        {
          "direction": "out",
          "name": "need",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "give",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "give_di",
          "type": "wire",
          "width": "[DW-1:0]"
        }
      ],
      "random_ff": [
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          "name": "DOES",
          "type": "wire",
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        },
        {
          "direction": "in",
          "name": "D",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CLK",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Q",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CLRN",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "SETN",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "SI",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "input",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "arbiter",
      "bc_fifo_basic",
      "clock_detect",
      "clock_switch2_basic",
      "clock_switch3_basic",
      "clock_switch4_basic",
      "clock_switch8_basic",
      "debouncer",
      "oc_fifo_basic",
      "random_ff"
    ]
  },
  {
    "namespace": "opencores",
    "name": "cdc_ufifo",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "cdc_ufifo generate an minimalist fifo. it can be 4 cells minimum. by default used implementation without ram only standart cells used , and it can be selected if need. most slowest stage is the output multiplexor.",
    "license": "Apache-2.0",
    "license_class": "permissive",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/cdc_ufifo.git",
    "tags": [
      "cdc",
      "clock",
      "crossing",
      "delay",
      "dffe",
      "domain",
      "ff",
      "prim",
      "pulse",
      "ufifo"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-05T10:26:01Z",
    "updated_at": "2010-12-02T13:30:18+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-05",
    "desc_source": "header",
    "top_ports": {
      "cdc_ufifo": [
        {
          "direction": "out",
          "name": "multiplexor",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "or",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "in_clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "d",
          "type": "wire",
          "width": "[lpm_width-1:0]"
        },
        {
          "direction": "out",
          "name": "q",
          "type": "wire",
          "width": "[lpm_width-1:0]"
        },
        {
          "direction": "out",
          "name": "ready",
          "type": "wire",
          "width": ""
        }
      ],
      "gray2bin": [
        {
          "direction": "out",
          "name": "bin",
          "type": "wire",
          "width": "[lpm_size-1:0]"
        },
        {
          "direction": "in",
          "name": "gray",
          "type": "wire",
          "width": "[lpm_size-1:0]"
        }
      ]
    },
    "top_modules": [
      "cdc_ufifo",
      "gray2bin"
    ]
  },
  {
    "namespace": "opencores",
    "name": "cfi_ctrl",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Top level of CFI controller with 32-bit Wishbone classic interface Intended to be used at about 66MHz with a 32MB CFI flash part with 16-bit data interface.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/cfi_ctrl.git",
    "tags": [
      "cfi",
      "control",
      "controller",
      "ctrl",
      "engine"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-05T10:26:01Z",
    "updated_at": "2011-10-23T12:05:51+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-05",
    "desc_source": "header",
    "top_ports": {
      "cfi_ctrl": [
        {
          "direction": "inout",
          "name": "flash_dq_io",
          "type": "wire",
          "width": "[flash_dq_width-1:0]"
        },
        {
          "direction": "out",
          "name": "flash_adr_o",
          "type": "wire",
          "width": "[flash_adr_width-1:0]"
        },
        {
          "direction": "out",
          "name": "flash_adv_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_ce_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_clk_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_oe_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_rst_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "flash_wait_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_we_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "flash_wp_n_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_clk_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_sel_i",
          "type": "wire",
          "width": "[3:0]"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "wire",
          "width": "[31:0]"
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_err_o",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "cfi_ctrl"
    ]
  },
  {
    "namespace": "opencores",
    "name": "copyblaze",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "PicoBlaze-compatible 8-bit microcontroller in VHDL-2008 (Adrien Trousson 2015+). Compact softcore with peripheral ecosystem (UART, GPIO) over Wishbone.",
    "license": "LGPL-2.1-only",
    "license_class": "weak-copyleft",
    "language": "vhdl-2008",
    "library": "work",
    "source_url": "https://github.com/freecores/copyblaze.git",
    "tags": [
      "asynchronous",
      "bancregister",
      "copyblaze",
      "decodecontrol",
      "ecosystem",
      "fulladder",
      "interrupt",
      "programcounter",
      "programflowcontrol",
      "scratchpad",
      "transmitter",
      "universal"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T22:57:14Z",
    "updated_at": "2011-12-25T11:08:26+00:00",
    "health_tier": "bronze",
    "last_verified_at": "2026-05-04",
    "desc_source": "verdict",
    "provides_packages": [
      "Usefull_Pkg"
    ],
    "top_ports": {
      "WBOPRT08": [
        {
          "direction": "out",
          "name": "ACK_O",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "CLK_I",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "RST_I",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "STB_I",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "WE_I",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "PRT_O",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        }
      ],
      "cp_copyBlaze_ecoSystem": [
        {
          "direction": "in",
          "name": "Clk_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Interrupt_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "Interrupt_Ack_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "IN_PORT_i",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "OUT_PORT_o",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "PORT_ID_o",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "READ_STROBE_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "WRITE_STROBE_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "Freeze_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "ADR_O",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "in",
          "name": "DAT_I",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "DAT_O",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "WE_O",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "SEL_O",
          "type": "std_ulogic_vector",
          "width": "1 downto 0"
        },
        {
          "direction": "out",
          "name": "STB_O",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "ACK_I",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "CYC_O",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "mux32": [
        {
          "direction": "in",
          "name": "input",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "output",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "sel",
          "type": "std_logic_vector",
          "width": "4 downto 0"
        }
      ],
      "sp_ram": [
        {
          "direction": "in",
          "name": "clka",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wea",
          "type": "std_logic_vector",
          "width": "0 downto 0"
        },
        {
          "direction": "in",
          "name": "addra",
          "type": "std_logic_vector",
          "width": "addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "dina",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "douta",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        }
      ],
      "wb_Np_ram": [
        {
          "direction": "in",
          "name": "wb_clk_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_rst_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb1_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb1_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb1_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb1_adr_i",
          "type": "std_logic_vector",
          "width": "addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb1_dat_i",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb1_dat_o",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb1_ack_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb2_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb2_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb2_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb2_adr_i",
          "type": "std_logic_vector",
          "width": "addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb2_dat_i",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb2_dat_o",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb2_ack_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb3_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb3_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb3_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb3_adr_i",
          "type": "std_logic_vector",
          "width": "addr_width-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb3_dat_i",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb3_dat_o",
          "type": "std_logic_vector",
          "width": "data_width-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb3_ack_o",
          "type": "std_logic",
          "width": ""
        }
      ],
      "wb_gpio": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_sel_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "iport",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "oport",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        }
      ],
      "wb_gpio_08": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "iport",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        },
        {
          "direction": "out",
          "name": "oport",
          "type": "std_ulogic_vector",
          "width": "7 downto 0"
        }
      ],
      "wb_scope": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_sel_i",
          "type": "std_logic_vector",
          "width": "3 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_irq_o",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "probe",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        }
      ],
      "wb_sram": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_dat_i",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "out",
          "name": "wb_dat_o",
          "type": "std_ulogic_vector",
          "width": "GEN_WIDTH_DATA-1 downto 0"
        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_ack_o",
          "type": "std_ulogic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_we_i",
          "type": "std_ulogic",
          "width": ""
        }
      ],
      "wb_timer": [
        {
          "direction": "in",
          "name": "clk",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_adr_i",
          "type": "std_logic_vector",
          "width": "31 downto 0"
        },
        {
          "direction": "in",
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        },
        {
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        },
        {
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          "name": "wb_sel_i",
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        },
        {
          "direction": "in",
          "name": "wb_cyc_i",
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          "width": ""
        },
        {
          "direction": "in",
          "name": "wb_stb_i",
          "type": "std_logic",
          "width": ""
        },
        {
          "direction": "out",
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        },
        {
          "direction": "in",
          "name": "wb_we_i",
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          "width": ""
        },
        {
          "direction": "out",
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          "width": ""
        },
        {
          "direction": "out",
          "name": "wb_irq1_o",
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          "width": ""
        }
      ],
      "wb_timer_8": [
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          "direction": "in",
          "name": "clk",
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        },
        {
          "direction": "in",
          "name": "reset",
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        },
        {
          "direction": "in",
          "name": "wb_adr_i",
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        },
        {
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          "name": "wb_dat_i",
          "type": "std_ulogic_vector",
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        },
        {
          "direction": "out",
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        {
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        },
        {
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        },
        {
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        },
        {
          "direction": "in",
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        },
        {
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        },
        {
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        }
      ],
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        },
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        },
        {
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        },
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        },
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          "direction": "out",
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        },
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        },
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          "width": ""
        },
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          "width": ""
        }
      ]
    },
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      "cp_copyBlaze_ecoSystem",
      "mux32",
      "sp_ram",
      "wb_Np_ram",
      "wb_gpio",
      "wb_gpio_08",
      "wb_scope",
      "wb_sram",
      "wb_timer",
      "wb_timer_8",
      "wb_uart",
      "wb_uart_8"
    ]
  },
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    ],
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      "tc"
    ],
    "role": "top",
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          "direction": "in",
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        {
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        {
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        {
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        },
        {
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        {
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        },
        {
          "direction": "out",
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      ]
    },
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    "latest": "master",
    "versions": [
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    "language": "vhdl-2008",
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      "schedule"
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    "desc_source": "verdict",
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        },
        {
          "direction": "in",
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        },
        {
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        {
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      "master"
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        {
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        {
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        {
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          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "l0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "v0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "A",
          "type": "wire",
          "width": "[`WIDTH : 0]"
        },
        {
          "direction": "out",
          "name": "C",
          "type": "wire",
          "width": "[`WIDTH : 0]"
        },
        {
          "direction": "in",
          "name": "a0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "c",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "done",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "c0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": "[193:0]"
        },
        {
          "direction": "in",
          "name": "S",
          "type": "wire",
          "width": "[`WIDTH+2:0]"
        },
        {
          "direction": "in",
          "name": "q",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "B",
          "type": "wire",
          "width": "[`WIDTH+2:0]"
        },
        {
          "direction": "in",
          "name": "aa",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[5:0]"
        }
      ],
      "func8": [
        {
          "direction": "in",
          "name": "v1",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "l1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "out",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "l0",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "v0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "A",
          "type": "wire",
          "width": "[`WIDTH : 0]"
        },
        {
          "direction": "out",
          "name": "C",
          "type": "wire",
          "width": "[`WIDTH : 0]"
        },
        {
          "direction": "in",
          "name": "a0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "c",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "a",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "reset",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "done",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "c0",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "in",
          "type": "wire",
          "width": "[193:0]"
        },
        {
          "direction": "in",
          "name": "S",
          "type": "wire",
          "width": "[`WIDTH+2:0]"
        },
        {
          "direction": "in",
          "name": "q",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "B",
          "type": "wire",
          "width": "[`WIDTH+2:0]"
        },
        {
          "direction": "in",
          "name": "aa",
          "type": "wire",
          "width": "[1:0]"
        },
        {
          "direction": "in",
          "name": "b",
          "type": "wire",
          "width": "[5:0]"
        }
      ],
      "func9": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x1",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "c",
          "type": "wire",
          "width": "[`SCALAR_WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "done",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x3",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "zero3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x2",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero2",
          "type": "wire",
          "width": ""
        }
      ],
      "point_add": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x1",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "c",
          "type": "wire",
          "width": "[`SCALAR_WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "done",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x3",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "zero3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x2",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero2",
          "type": "wire",
          "width": ""
        }
      ],
      "point_scalar_mult": [
        {
          "direction": "in",
          "name": "clk",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x1",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero1",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "c",
          "type": "wire",
          "width": "[`SCALAR_WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "done",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "out",
          "name": "x3",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "out",
          "name": "zero3",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "of",
          "type": "wire",
          "width": ""
        },
        {
          "direction": "in",
          "name": "x2",
          "type": "wire",
          "width": "[`WIDTH:0]"
        },
        {
          "direction": "in",
          "name": "zero2",
          "type": "wire",
          "width": ""
        }
      ]
    },
    "top_modules": [
      "f3_add1",
      "f3_mult",
      "f3_sub",
      "f3_sub1",
      "f3m_add3",
      "f3m_add4",
      "f3m_cubic",
      "f3m_inv",
      "f3m_mult",
      "f3m_mult3",
      "f3m_mux3",
      "f3m_mux6",
      "f3m_neg",
      "f3m_nine",
      "f3m_sub",
      "func1",
      "func10",
      "func11",
      "func2",
      "func3",
      "func4",
      "func5",
      "func7",
      "func8",
      "func9",
      "point_add",
      "point_scalar_mult"
    ]
  },
  {
    "namespace": "opencores",
    "name": "ethernet_tri_mode",
    "latest": "master",
    "versions": [
      "master"
    ],
    "description": "Tri-mode 10/100/1000 Mbps Ethernet MAC with GMII PHY interface (Jon Gao, OpenCores 2005-2018). 32-bit OpenCores streaming user bus, Wishbone-style CSR access, includes RMON statistics.",
    "license": "LGPL-2.1-or-later",
    "license_class": "weak-copyleft",
    "language": "verilog",
    "library": "work",
    "source_url": "https://github.com/freecores/ethernet_tri_mode.git",
    "tags": [
      "access",
      "broadcast",
      "control",
      "controller",
      "cyclic",
      "physical",
      "receive",
      "receiver",
      "redundancy",
      "register",
      "transmit",
      "transmitter"
    ],
    "role": "top",
    "library_deps": [],
    "created_at": "2026-05-03T22:57