[ { "namespace": "alex-forencich", "name": "verilog-ethernet", "latest": "master", "versions": [ "master" ], "description": "Verilog Ethernet MAC + IP/UDP stack supporting 1G/10G/25G/40G/100G with both Intel and Xilinx primitives (Alex Forencich). Deprecated upstream \u2014 author moved active development to fpganinja/taxi (CERN-OHL-S-2.0).", "license": "MIT", "language": "verilog", "library": "work", "source_url": "https://github.com/alexforencich/verilog-ethernet.git", "tags": [ "arbitration", "controller", "deinterleave", "demultiplexer", "independent", "interface", "interleave", "multiplexer", "resolution", "synchronizer", "synchronous", "transmitter" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T22:57:14Z", "updated_at": "2025-02-27T15:50:25-08:00", "status": "deprecated-upstream", "successor": "fpganinja/taxi", "health_tier": "silver", "contract_url": "https://github.com/routertl/ip-index/blob/main/contracts/eth_mac_1g_requirements.yml", "last_verified_at": "2026-05-04", "desc_source": "verdict", "contract": { "traits": { "rx_strips_fcs": true, "tx_user_frame_includes_fcs": false }, "defects": [] }, "top_ports": { "axis_eth_fcs": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "output_fcs", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "output_fcs_valid", "type": "wire", "width": "" } ], "axis_eth_fcs_check": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "out", "name": "error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "axis_eth_fcs_check_64": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "s_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "m_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "out", "name": "error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "axis_eth_fcs_insert": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "axis_eth_fcs_insert_64": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "s_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "m_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "in", "name": "k", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "eth_axis_rx": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "out", "name": "error_header_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "eth_axis_tx": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "busy", "type": "wire", "width": "" }, { "direction": "out", "name": "AXI", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "eth_demux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tid", "type": "wire", "width": "[ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdest", "type": "wire", "width": "[DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_hdr_valid", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "in", "name": "m_eth_hdr_ready", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[M_COUNT*48-1:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[M_COUNT*48-1:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[M_COUNT*16-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdata", "type": "wire", "width": "[M_COUNT*DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tkeep", "type": "wire", "width": "[M_COUNT*KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "in", "name": "m_eth_payload_axis_tready", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tlast", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tid", "type": "wire", "width": "[M_COUNT*ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdest", "type": "wire", "width": "[M_COUNT*DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tuser", "type": "wire", "width": "[M_COUNT*USER_WIDTH-1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "drop", "type": "wire", "width": "" }, { "direction": "in", "name": "select", "type": "wire", "width": "[$clog2(M_COUNT)-1:0]" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "eth_mac_10g_fifo": [ { "direction": "in", "name": "rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "[TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_96", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_tag", "type": "wire", "width": "[PTP_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tx_ptp_ts_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "[RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "xgmii_rxd", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "xgmii_rxc", "type": "wire", "width": "[CTRL_WIDTH-1:0]" }, { "direction": "out", "name": "xgmii_txd", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "xgmii_txc", "type": "wire", "width": "[CTRL_WIDTH-1:0]" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_ts_96", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "ptp_ts_step", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" } ], "eth_mac_1g_fifo": [ { "direction": "in", "name": "rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "gmii_rxd", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "gmii_rx_dv", "type": "wire", "width": "" }, { "direction": "in", "name": "gmii_rx_er", "type": "wire", "width": "" }, { "direction": "out", "name": "gmii_txd", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "gmii_tx_en", "type": "wire", "width": "" }, { "direction": "out", "name": "gmii_tx_er", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_mii_select", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_mii_select", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" } ], "eth_mac_1g_gmii_fifo": [ { "direction": "in", "name": "style", "type": "wire", "width": "" }, { "direction": "in", "name": "gtx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "gtx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "gmii_rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "gmii_rxd", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "gmii_rx_dv", "type": "wire", "width": "" }, { "direction": "in", "name": "gmii_rx_er", "type": "wire", "width": "" }, { "direction": "in", "name": "mii_tx_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "gmii_tx_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "gmii_txd", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "gmii_tx_en", "type": "wire", "width": "" }, { "direction": "out", "name": "gmii_tx_er", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "speed", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" } ], "eth_mac_1g_rgmii_fifo": [ { "direction": "in", "name": "style", "type": "wire", "width": "" }, { "direction": "in", "name": "gtx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "gtx_clk90", "type": "wire", "width": "" }, { "direction": "in", "name": "gtx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "rgmii_rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rgmii_rxd", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rgmii_rx_ctl", "type": "wire", "width": "" }, { "direction": "out", "name": "rgmii_tx_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "rgmii_txd", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "rgmii_tx_ctl", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "speed", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" } ], "eth_mac_mii_fifo": [ { "direction": "in", "name": "style", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "mii_rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "mii_rxd", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "mii_rx_dv", "type": "wire", "width": "" }, { "direction": "in", "name": "mii_rx_er", "type": "wire", "width": "" }, { "direction": "in", "name": "mii_tx_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "mii_txd", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "mii_tx_en", "type": "wire", "width": "" }, { "direction": "out", "name": "mii_tx_er", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" } ], "eth_mac_phy_10g_fifo": [ { "direction": "in", "name": "rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "logic_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "tx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_axis_tuser", "type": "wire", "width": "[TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_96", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_tag", "type": "wire", "width": "[PTP_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_ptp_ts_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tx_ptp_ts_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tdata", "type": "wire", "width": "[AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tkeep", "type": "wire", "width": "[AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "rx_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_axis_tuser", "type": "wire", "width": "[RX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_tx_data", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_tx_hdr", "type": "wire", "width": "[HDR_WIDTH-1:0]" }, { "direction": "in", "name": "serdes_rx_data", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "serdes_rx_hdr", "type": "wire", "width": "[HDR_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_rx_bitslip", "type": "wire", "width": "" }, { "direction": "out", "name": "serdes_rx_reset_req", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_error_underflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_bad_fcs", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_bad_block", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_block_lock", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_high_ber", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_status", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_overflow", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_bad_frame", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_fifo_good_frame", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_ts_96", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "ptp_ts_step", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_ifg", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "cfg_tx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_tx_prbs31_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_prbs31_enable", "type": "wire", "width": "" } ], "eth_mux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_hdr_valid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_eth_hdr_ready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdata", "type": "wire", "width": "[S_COUNT*DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tkeep", "type": "wire", "width": "[S_COUNT*KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tvalid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_eth_payload_axis_tready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tlast", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tid", "type": "wire", "width": "[S_COUNT*ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdest", "type": "wire", "width": "[S_COUNT*DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tuser", "type": "wire", "width": "[S_COUNT*USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tid", "type": "wire", "width": "[ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdest", "type": "wire", "width": "[DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "select", "type": "wire", "width": "[$clog2(S_COUNT)-1:0]" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "eth_phy_10g": [ { "direction": "in", "name": "rx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "xgmii_txd", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "xgmii_txc", "type": "wire", "width": "[CTRL_WIDTH-1:0]" }, { "direction": "out", "name": "xgmii_rxd", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "xgmii_rxc", "type": "wire", "width": "[CTRL_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_tx_data", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_tx_hdr", "type": "wire", "width": "[HDR_WIDTH-1:0]" }, { "direction": "in", "name": "serdes_rx_data", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "serdes_rx_hdr", "type": "wire", "width": "[HDR_WIDTH-1:0]" }, { "direction": "out", "name": "serdes_rx_bitslip", "type": "wire", "width": "" }, { "direction": "out", "name": "serdes_rx_reset_req", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_bad_block", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_error_count", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "rx_bad_block", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_sequence_error", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_block_lock", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_high_ber", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_status", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_tx_prbs31_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "cfg_rx_prbs31_enable", "type": "wire", "width": "" } ], "ip_demux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tid", "type": "wire", "width": "[ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdest", "type": "wire", "width": "[DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_hdr_valid", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "in", "name": "m_ip_hdr_ready", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[M_COUNT*48-1:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[M_COUNT*48-1:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[M_COUNT*16-1:0]" }, { "direction": "out", "name": "m_ip_version", "type": "wire", "width": "[M_COUNT*4-1:0]" }, { "direction": "out", "name": "m_ip_ihl", "type": "wire", "width": "[M_COUNT*4-1:0]" }, { "direction": "out", "name": "m_ip_dscp", "type": "wire", "width": "[M_COUNT*6-1:0]" }, { "direction": "out", "name": "m_ip_ecn", "type": "wire", "width": "[M_COUNT*2-1:0]" }, { "direction": "out", "name": "m_ip_length", "type": "wire", "width": "[M_COUNT*16-1:0]" }, { "direction": "out", "name": "m_ip_identification", "type": "wire", "width": "[M_COUNT*16-1:0]" }, { "direction": "out", "name": "m_ip_flags", "type": "wire", "width": "[M_COUNT*3-1:0]" }, { "direction": "out", "name": "m_ip_fragment_offset", "type": "wire", "width": "[M_COUNT*13-1:0]" }, { "direction": "out", "name": "m_ip_ttl", "type": "wire", "width": "[M_COUNT*8-1:0]" }, { "direction": "out", "name": "m_ip_protocol", "type": "wire", "width": "[M_COUNT*8-1:0]" }, { "direction": "out", "name": "m_ip_header_checksum", "type": "wire", "width": "[M_COUNT*16-1:0]" }, { "direction": "out", "name": "m_ip_source_ip", "type": "wire", "width": "[M_COUNT*32-1:0]" }, { "direction": "out", "name": "m_ip_dest_ip", "type": "wire", "width": "[M_COUNT*32-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdata", "type": "wire", "width": "[M_COUNT*DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tkeep", "type": "wire", "width": "[M_COUNT*KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "in", "name": "m_ip_payload_axis_tready", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tlast", "type": "wire", "width": "[M_COUNT-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tid", "type": "wire", "width": "[M_COUNT*ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdest", "type": "wire", "width": "[M_COUNT*DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tuser", "type": "wire", "width": "[M_COUNT*USER_WIDTH-1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "drop", "type": "wire", "width": "" }, { "direction": "in", "name": "select", "type": "wire", "width": "[$clog2(M_COUNT)-1:0]" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "ip_mux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_hdr_valid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_ip_hdr_ready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_version", "type": "wire", "width": "[S_COUNT*4-1:0]" }, { "direction": "in", "name": "s_ip_ihl", "type": "wire", "width": "[S_COUNT*4-1:0]" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[S_COUNT*6-1:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[S_COUNT*2-1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_identification", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_flags", "type": "wire", "width": "[S_COUNT*3-1:0]" }, { "direction": "in", "name": "s_ip_fragment_offset", "type": "wire", "width": "[S_COUNT*13-1:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[S_COUNT*8-1:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[S_COUNT*8-1:0]" }, { "direction": "in", "name": "s_ip_header_checksum", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[S_COUNT*32-1:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[S_COUNT*32-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdata", "type": "wire", "width": "[S_COUNT*DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tkeep", "type": "wire", "width": "[S_COUNT*KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tvalid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_ip_payload_axis_tready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tlast", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tid", "type": "wire", "width": "[S_COUNT*ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdest", "type": "wire", "width": "[S_COUNT*DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tuser", "type": "wire", "width": "[S_COUNT*USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tid", "type": "wire", "width": "[ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdest", "type": "wire", "width": "[DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "select", "type": "wire", "width": "[$clog2(S_COUNT)-1:0]" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "ptp_clock": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_96", "type": "wire", "width": "[95:0]" }, { "direction": "in", "name": "input_ts_96_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_64", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "input_ts_64_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "input_period_ns", "type": "wire", "width": "[PERIOD_NS_WIDTH-1:0]" }, { "direction": "in", "name": "input_period_fns", "type": "wire", "width": "[FNS_WIDTH-1:0]" }, { "direction": "in", "name": "input_period_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "input_adj_ns", "type": "wire", "width": "[OFFSET_NS_WIDTH-1:0]" }, { "direction": "in", "name": "input_adj_fns", "type": "wire", "width": "[FNS_WIDTH-1:0]" }, { "direction": "in", "name": "input_adj_count", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "input_adj_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_adj_active", "type": "wire", "width": "" }, { "direction": "in", "name": "input_drift_ns", "type": "wire", "width": "[DRIFT_NS_WIDTH-1:0]" }, { "direction": "in", "name": "input_drift_fns", "type": "wire", "width": "[FNS_WIDTH-1:0]" }, { "direction": "in", "name": "input_drift_rate", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "input_drift_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "output_ts_96", "type": "wire", "width": "[95:0]" }, { "direction": "out", "name": "output_ts_64", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "output_ts_step", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pps", "type": "wire", "width": "" } ], "ptp_perout": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_96", "type": "wire", "width": "[95:0]" }, { "direction": "in", "name": "input_ts_step", "type": "wire", "width": "" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "input_start", "type": "wire", "width": "[95:0]" }, { "direction": "in", "name": "input_start_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "input_period", "type": "wire", "width": "[95:0]" }, { "direction": "in", "name": "input_period_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "input_width", "type": "wire", "width": "[95:0]" }, { "direction": "in", "name": "input_width_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "locked", "type": "wire", "width": "" }, { "direction": "out", "name": "error", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pulse", "type": "wire", "width": "" } ], "ptp_tag_insert": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tag", "type": "wire", "width": "[TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tag_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axis_tag_ready", "type": "wire", "width": "" } ], "ptp_td_leaf": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_td_sdi", "type": "wire", "width": "" }, { "direction": "out", "name": "output_ts_rel", "type": "wire", "width": "[TS_REL_W-1:0]" }, { "direction": "out", "name": "output_ts_rel_step", "type": "wire", "width": "" }, { "direction": "out", "name": "output_ts_tod", "type": "wire", "width": "[TS_TOD_W-1:0]" }, { "direction": "out", "name": "output_ts_tod_step", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pps", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pps_str", "type": "wire", "width": "" }, { "direction": "out", "name": "locked", "type": "wire", "width": "" }, { "direction": "in", "name": "path", "type": "wire", "width": "" }, { "direction": "out", "name": "case", "type": "wire", "width": "" }, { "direction": "in", "name": "stepped", "type": "wire", "width": "" } ], "ptp_td_phc": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_tod_s", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "input_ts_tod_ns", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "input_ts_tod_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_ts_tod_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_tod_offset_ns", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "input_ts_tod_offset_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_ts_tod_offset_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_rel_ns", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "input_ts_rel_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_ts_rel_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_rel_offset_ns", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "input_ts_rel_offset_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_ts_rel_offset_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_offset_fns", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "input_ts_offset_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_ts_offset_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_period_ns", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "input_period_fns", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "input_period_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_period_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "input_drift_num", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "input_drift_denom", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "input_drift_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "input_drift_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_td_sdo", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pps", "type": "wire", "width": "" }, { "direction": "out", "name": "output_pps_str", "type": "wire", "width": "" } ], "ptp_td_rel2tod": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_td_sdi", "type": "wire", "width": "" }, { "direction": "in", "name": "input_ts_rel", "type": "wire", "width": "[TS_REL_W-1:0]" }, { "direction": "in", "name": "input_ts_tag", "type": "wire", "width": "[TS_TAG_W-1:0]" }, { "direction": "in", "name": "input_ts_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "output_ts_tod", "type": "wire", "width": "[TS_TOD_W-1:0]" }, { "direction": "out", "name": "output_ts_tag", "type": "wire", "width": "[TS_TAG_W-1:0]" }, { "direction": "out", "name": "output_ts_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "path", "type": "wire", "width": "" } ], "ptp_ts_extract": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_ts", "type": "wire", "width": "[TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_ts_valid", "type": "wire", "width": "" } ], "ssio_ddr_in_diff": [ { "direction": "in", "name": "style", "type": "wire", "width": "" }, { "direction": "in", "name": "input_clk_p", "type": "wire", "width": "" }, { "direction": "in", "name": "input_clk_n", "type": "wire", "width": "" }, { "direction": "in", "name": "input_d_p", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "in", "name": "input_d_n", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "output_q1", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_q2", "type": "wire", "width": "[WIDTH-1:0]" } ], "ssio_ddr_out_diff": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "clk90", "type": "wire", "width": "" }, { "direction": "in", "name": "input_d1", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "in", "name": "input_d2", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_clk_p", "type": "wire", "width": "" }, { "direction": "out", "name": "output_clk_n", "type": "wire", "width": "" }, { "direction": "out", "name": "output_q_p", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_q_n", "type": "wire", "width": "[WIDTH-1:0]" } ], "ssio_sdr_in_diff": [ { "direction": "in", "name": "style", "type": "wire", "width": "" }, { "direction": "in", "name": "input_clk_p", "type": "wire", "width": "" }, { "direction": "in", "name": "input_clk_n", "type": "wire", "width": "" }, { "direction": "in", "name": "input_d_p", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "in", "name": "input_d_n", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "output_q", "type": "wire", "width": "[WIDTH-1:0]" } ], "ssio_sdr_out_diff": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "input_d", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_clk_p", "type": "wire", "width": "" }, { "direction": "out", "name": "output_clk_n", "type": "wire", "width": "" }, { "direction": "out", "name": "output_q_p", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "output_q_n", "type": "wire", "width": "[WIDTH-1:0]" } ], "udp_arb_mux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_hdr_valid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_udp_hdr_ready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[S_COUNT*48-1:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_version", "type": "wire", "width": "[S_COUNT*4-1:0]" }, { "direction": "in", "name": "s_ip_ihl", "type": "wire", "width": "[S_COUNT*4-1:0]" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[S_COUNT*6-1:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[S_COUNT*2-1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_identification", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_flags", "type": "wire", "width": "[S_COUNT*3-1:0]" }, { "direction": "in", "name": "s_ip_fragment_offset", "type": "wire", "width": "[S_COUNT*13-1:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[S_COUNT*8-1:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[S_COUNT*8-1:0]" }, { "direction": "in", "name": "s_ip_header_checksum", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[S_COUNT*32-1:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[S_COUNT*32-1:0]" }, { "direction": "in", "name": "s_udp_source_port", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_udp_dest_port", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_udp_length", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_udp_checksum", "type": "wire", "width": "[S_COUNT*16-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tdata", "type": "wire", "width": "[S_COUNT*DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tkeep", "type": "wire", "width": "[S_COUNT*KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tvalid", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "out", "name": "s_udp_payload_axis_tready", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tlast", "type": "wire", "width": "[S_COUNT-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tid", "type": "wire", "width": "[S_COUNT*ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tdest", "type": "wire", "width": "[S_COUNT*DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tuser", "type": "wire", "width": "[S_COUNT*USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tdata", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tkeep", "type": "wire", "width": "[KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tid", "type": "wire", "width": "[ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tdest", "type": "wire", "width": "[DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tuser", "type": "wire", "width": "[USER_WIDTH-1:0]" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "registers", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" } ], "udp_complete": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_ip_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_ip_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_udp_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_udp_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_udp_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_udp_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_udp_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_udp_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_udp_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_udp_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_udp_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_udp_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_udp_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_udp_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_udp_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_udp_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tdata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_tx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_header_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_invalid_header", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_invalid_checksum", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_error_arp_failed", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_error_header_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_tx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "in", "name": "local_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "local_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "gateway_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "subnet_mask", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clear_arp_cache", "type": "wire", "width": "" }, { "direction": "in", "name": "classifier", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" }, { "direction": "out", "name": "arbiter", "type": "wire", "width": "" } ], "udp_complete_64": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_eth_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_eth_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_eth_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_ip_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_ip_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_ip_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_ip_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_ip_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_ip_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_udp_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_udp_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_udp_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_udp_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_udp_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_udp_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "m_udp_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_udp_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_udp_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "m_udp_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_udp_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_udp_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "m_udp_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_udp_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tdata", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tkeep", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_udp_payload_axis_tvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_udp_payload_axis_tready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tlast", "type": "wire", "width": "" }, { "direction": "out", "name": "m_udp_payload_axis_tuser", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_tx_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_header_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_invalid_header", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_rx_error_invalid_checksum", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "ip_tx_error_arp_failed", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_error_header_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_rx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "out", "name": "udp_tx_error_payload_early_termination", "type": "wire", "width": "" }, { "direction": "in", "name": "local_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "local_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "gateway_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "subnet_mask", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clear_arp_cache", "type": "wire", "width": "" }, { "direction": "in", "name": "classifier", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" }, { "direction": "out", "name": "arbiter", "type": "wire", "width": "" } ], "udp_demux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "s_udp_hdr_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_udp_hdr_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_eth_dest_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_src_mac", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "s_eth_type", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_version", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_ip_ihl", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_ip_dscp", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "s_ip_ecn", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "s_ip_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_identification", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_flags", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_ip_fragment_offset", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "s_ip_ttl", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_protocol", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "s_ip_header_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_ip_source_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_ip_dest_ip", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_udp_source_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_dest_port", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_length", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_checksum", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "s_udp_payload_axis_tdata", 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"in", "name": "rx_phy_kchar_3", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_full_3", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_empty_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_align_en_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_polarity_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_powerdown_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_bit_reversal_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_byte_reversal_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_analogreset_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_digitalreset_3", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_locked_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_cal_busy_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_valid_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_data_4", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "rx_phy_disperr_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_deterr_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_kchar_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_full_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_empty_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_align_en_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_polarity_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_powerdown_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_bit_reversal_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_byte_reversal_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_analogreset_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_digitalreset_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_locked_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_cal_busy_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_valid_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_data_5", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "rx_phy_disperr_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_deterr_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_kchar_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_full_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_empty_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_align_en_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_polarity_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_powerdown_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_bit_reversal_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_byte_reversal_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_analogreset_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_digitalreset_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_locked_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_cal_busy_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_valid_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_data_6", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "rx_phy_disperr_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_deterr_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_kchar_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_full_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_empty_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_align_en_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_polarity_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_powerdown_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_bit_reversal_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_byte_reversal_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_analogreset_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_digitalreset_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_locked_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_cal_busy_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_valid_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_data_7", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "rx_phy_disperr_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_deterr_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_kchar_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "rx_phy_full_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_phy_empty_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_align_en_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_polarity_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_lane_powerdown_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_bit_reversal_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_byte_reversal_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_analogreset_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_phy_digitalreset_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_core_analogreset", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "rx_core_digitalreset", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "rx_core_locked", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "rx_core_cal_busy", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "tx_ip_cal_busy", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "tx_ip_full", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "tx_ip_empty", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "tx_ip_data", "type": "wire", "width": "[((NUM_OF_LANES*32)-1):0]" }, { "direction": "in", "name": "tx_ip_kchar", "type": "wire", "width": "[((NUM_OF_LANES* 4)-1):0]" }, { "direction": "in", "name": "tx_ip_elecidle", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "tx_ip_lane_polarity", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "tx_ip_lane_powerdown", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "tx_ip_bit_reversal", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_ip_byte_reversal", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_0", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_0", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_0", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_0", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_0", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_0", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_1", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_2", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_2", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_3", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_3", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_4", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_5", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_6", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_cal_busy_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_full_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_phy_empty_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_data_7", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "tx_phy_kchar_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "tx_phy_elecidle_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_polarity_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_lane_powerdown_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_bit_reversal_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_byte_reversal_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_analogreset_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_phy_digitalreset_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_core_analogreset", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "in", "name": "tx_core_digitalreset", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" }, { "direction": "out", "name": "tx_core_cal_busy", "type": "wire", "width": "[((NUM_OF_LANES* 1)-1):0]" } ] } }, { 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"direction": "out", "name": "up_ch_prbssel_1", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_1", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_2", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_2", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_2", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_3", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_3", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_3", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_5", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_5", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_6", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_6", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_7", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_7", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_8", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_9", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_9", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_9", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_10", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_10", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_10", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_11", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_11", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_11", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_12", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_13", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_13", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_13", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_14", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_14", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_14", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_15", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_15", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_15", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_16", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_17", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_17", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_17", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_18", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_18", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_18", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_19", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_19", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_19", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_20", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_21", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_21", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_21", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_22", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_22", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_22", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_23", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_23", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_23", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_cm_wr_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_cm_ready_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_24", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_25", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_25", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_25", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_26", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_26", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_26", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_27", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_27", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_postcursor_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_tx_precursor_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "up_ch_enb_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_addr_27", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_ch_wr_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_wdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_rdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_ch_ready_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_cm_enb_28", "type": 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"type": "wire", "width": "" }, { "direction": "out", "name": "up_es_enb_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_addr_29", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "up_es_wr_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_reset_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_es_wdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_rdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "up_es_ready_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_pll_locked_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rst_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_user_ready_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_rst_done_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbsforceerr_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_prbssel_29", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "up_ch_prbscntreset_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbserr_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_prbslocked_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_ch_bufstatus_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_bufstatus_rst_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_lpm_dfe_n_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_ch_rate_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_sys_clk_sel_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "up_ch_out_clk_sel_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "out", "name": "up_ch_tx_diffctrl_29", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": 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"direction": "out", "name": "m_axi_arburst", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "m_axi_arlock", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axi_arcache", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_axi_arprot", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_axi_arvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axi_arready", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axi_rid", "type": "wire", "width": "[AXI_ID_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_rdata", "type": "wire", "width": "[AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "m_axi_rlast", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axi_rvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axi_rready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_ctrl_awaddr", "type": "wire", "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_ctrl_awprot", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_axil_ctrl_awvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_ctrl_awready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_ctrl_wdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_ctrl_wstrb", "type": "wire", "width": "[AXIL_CTRL_STRB_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_ctrl_wvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_ctrl_wready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_ctrl_bresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axil_ctrl_bvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_ctrl_bready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_ctrl_araddr", "type": "wire", "width": "[AXIL_CTRL_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_ctrl_arprot", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_axil_ctrl_arvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_ctrl_arready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_ctrl_rdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "s_axil_ctrl_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axil_ctrl_rvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_ctrl_rready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axil_csr_awaddr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axil_csr_awprot", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_axil_csr_awvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axil_csr_awready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axil_csr_wdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axil_csr_wstrb", "type": "wire", "width": "[AXIL_CTRL_STRB_WIDTH-1:0]" }, { "direction": "out", "name": "m_axil_csr_wvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axil_csr_wready", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axil_csr_bresp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "m_axil_csr_bvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axil_csr_bready", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axil_csr_araddr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axil_csr_arprot", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_axil_csr_arvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axil_csr_arready", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axil_csr_rdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "m_axil_csr_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "m_axil_csr_rvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axil_csr_rready", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_wr_addr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_reg_wr_data", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_reg_wr_strb", "type": "wire", "width": "[AXIL_CTRL_STRB_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_reg_wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_reg_wr_wait", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_reg_wr_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_rd_addr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_reg_rd_en", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_reg_rd_data", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_reg_rd_wait", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_reg_rd_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_td_sd", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_pps", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_pps_str", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sync_locked", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sync_ts_rel", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "ptp_sync_ts_rel_step", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sync_ts_tod", "type": "wire", "width": "[96:0]" }, { "direction": "out", "name": "ptp_sync_ts_tod_step", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sync_pps", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sync_pps_str", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_perout_locked", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "out", "name": "ptp_perout_error", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "out", "name": "ptp_perout_pulse", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "tx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "tx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "tx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "tx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "tx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "tx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tx_cpl_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tx_cpl_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_tx_cpl_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_tx_cpl_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "tx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "tx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "tx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "tx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "tx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "tx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "tx_fc_quanta_clk_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "rx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "rx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "rx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "rx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "rx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "rx_lfc_ack", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "rx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "rx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "rx_pfc_ack", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "rx_fc_quanta_clk_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "ddr_clk", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "ddr_rst", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awid", "type": "wire", "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awaddr", "type": "wire", "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awlen", "type": "wire", "width": "[DDR_CH*8-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awsize", "type": "wire", "width": "[DDR_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awburst", "type": "wire", "width": "[DDR_CH*2-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awlock", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awcache", "type": "wire", "width": "[DDR_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awprot", "type": "wire", "width": "[DDR_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awqos", "type": "wire", "width": "[DDR_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awuser", "type": "wire", "width": "[DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awvalid", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_awready", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_wdata", "type": "wire", "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_wstrb", "type": "wire", "width": "[DDR_CH*AXI_DDR_STRB_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_wlast", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_wuser", "type": "wire", "width": "[DDR_CH*AXI_DDR_WUSER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_wvalid", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_wready", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_bid", "type": "wire", "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_bresp", "type": "wire", "width": "[DDR_CH*2-1:0]" }, { "direction": "in", "name": "m_axi_ddr_buser", "type": "wire", "width": "[DDR_CH*AXI_DDR_BUSER_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_bvalid", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_bready", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arid", "type": "wire", "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_araddr", "type": "wire", "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arlen", "type": "wire", "width": "[DDR_CH*8-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arsize", "type": "wire", "width": "[DDR_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arburst", "type": "wire", "width": "[DDR_CH*2-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arlock", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arcache", "type": "wire", "width": "[DDR_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arprot", "type": "wire", "width": "[DDR_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arqos", "type": "wire", "width": "[DDR_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_ddr_aruser", "type": "wire", "width": "[DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_arvalid", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_arready", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_rid", "type": "wire", "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_rdata", "type": "wire", "width": "[DDR_CH*AXI_DDR_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_rresp", "type": "wire", "width": "[DDR_CH*2-1:0]" }, { "direction": "in", "name": "m_axi_ddr_rlast", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_ruser", "type": "wire", "width": "[DDR_CH*AXI_DDR_RUSER_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_ddr_rvalid", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_rready", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "ddr_status", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "hbm_clk", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "in", "name": "hbm_rst", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awid", "type": "wire", "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awaddr", "type": "wire", "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awlen", "type": "wire", "width": "[HBM_CH*8-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awsize", "type": "wire", "width": "[HBM_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awburst", "type": "wire", "width": "[HBM_CH*2-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awlock", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awcache", "type": "wire", "width": "[HBM_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awprot", "type": "wire", "width": "[HBM_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awqos", "type": "wire", "width": "[HBM_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awuser", "type": "wire", "width": "[HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_awvalid", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "in", "name": "m_axi_hbm_awready", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_wdata", "type": "wire", "width": "[HBM_CH*AXI_HBM_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_wstrb", "type": "wire", "width": "[HBM_CH*AXI_HBM_STRB_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_wlast", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_wuser", "type": "wire", "width": "[HBM_CH*AXI_HBM_WUSER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_wvalid", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "in", "name": "m_axi_hbm_wready", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "in", "name": "m_axi_hbm_bid", "type": "wire", "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_hbm_bresp", "type": "wire", "width": "[HBM_CH*2-1:0]" }, { "direction": "in", "name": "m_axi_hbm_buser", "type": "wire", "width": "[HBM_CH*AXI_HBM_BUSER_WIDTH-1:0]" }, { "direction": "in", "name": "m_axi_hbm_bvalid", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_bready", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arid", "type": "wire", "width": "[HBM_CH*AXI_HBM_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_araddr", "type": "wire", "width": "[HBM_CH*AXI_HBM_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arlen", "type": "wire", "width": "[HBM_CH*8-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arsize", "type": "wire", "width": "[HBM_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arburst", "type": "wire", "width": "[HBM_CH*2-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arlock", "type": "wire", "width": "[HBM_CH-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arcache", "type": "wire", "width": "[HBM_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arprot", "type": "wire", "width": "[HBM_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_hbm_arqos", "type": "wire", "width": "[HBM_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_hbm_aruser", "type": "wire", "width": "[HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0]" }, { "direction": "out", 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"direction": "in", "name": "s_axil_csr_araddr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_csr_arprot", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_axil_csr_arvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_arready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_rdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "s_axil_csr_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axil_csr_rvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_csr_rready", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_td_sd", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_locked", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_rel", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "ptp_sync_ts_rel_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_tod", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "ptp_sync_ts_tod_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_perout_locked", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_error", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_pulse", "type": "wire", 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"wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_ptp_ts_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_tx_fc_quanta_clk_en", "type": "wire", "width": "" }, { "direction": "out", "name": "axis_eth_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "eth_rx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_ack", "type": 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"in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "led", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "sfp_led", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sfp_rx_p", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_rx_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sfp_tx_p", "type": "wire", "width": "" }, { "direction": "out", "name": "sfp_tx_n", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_mgt_refclk_p", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_mgt_refclk_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sfp_tx_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_tx_fault", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_rx_los", "type": "wire", "width": "" }, { "direction": "in", "name": "sfp_mod_abs", "type": "wire", "width": "" }, { "direction": "in", "name": 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"name": "s_axil_csr_awaddr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_csr_awprot", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_axil_csr_awvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_awready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_csr_wdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_csr_wstrb", "type": "wire", "width": "[AXIL_CTRL_STRB_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_csr_wvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_wready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_bresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axil_csr_bvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_csr_bready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_csr_araddr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "s_axil_csr_arprot", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "s_axil_csr_arvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_arready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axil_csr_rdata", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "s_axil_csr_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axil_csr_rvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axil_csr_rready", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "out", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_td_sd", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_locked", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_rel", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "ptp_sync_ts_rel_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_tod", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "ptp_sync_ts_tod_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_perout_locked", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_error", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_pulse", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "eth_tx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "eth_rx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_ptp_ts_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_tx_fc_quanta_clk_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "eth_rx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_ack", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_rx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "eth_rx_pfc_ack", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_rx_fc_quanta_clk_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "scl_i", "type": "wire", "width": "" }, { "direction": "out", "name": "scl_o", "type": "wire", "width": "" }, { "direction": "out", "name": "scl_t", "type": "wire", "width": "" }, { "direction": "in", "name": "sda_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sda_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sda_t", "type": "wire", "width": "" }, { "direction": "out", "name": "frequency", "type": "wire", "width": "" } ] } }, { "namespace": "analog-devices", "name": "ethernet_vcu118", "latest": "3dc381cf791c", "versions": [ "3dc381cf791c", "HEAD", "1336749ccfa9", "ca0618ef7b4f", "7b364c5dfd5e", "0.0.0" ], "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. The original file can be refereed", "license": "ADIBSD OR GPL-2.0-only", "language": "verilog", "library": "work", "source_url": "https://github.com/analogdevicesinc/hdl.git", "tags": [ "ethernet", "vcu118" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-13T08:20:05+00:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "axi_ctrlif" }, { "library": "work", "package": "axi_streaming_dma_rx_fifo" }, { "library": "work", "package": "axi_streaming_dma_tx_fifo" }, { "library": "work", "package": "dma_fifo" }, { "library": "work", "package": "fifo_synchronizer" }, { "library": "work", "package": "i2s_clkgen" }, { "library": "work", "package": "i2s_controller" }, { "library": "work", "package": "i2s_rx" }, { "library": "work", "package": "i2s_tx" }, { "library": "work", "package": "pl330_dma_fifo" } ], "top_ports": { "ethernet_vcu118": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_125mhz", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_125mhz", "type": "wire", "width": "" }, { "direction": "in", "name": "qsfp_drp_clk", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "qsfp_drp_rst", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "ctrl_reg_wr_addr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_reg_wr_data", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_reg_wr_strb", "type": "wire", "width": "[AXIL_CTRL_STRB_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_reg_wr_en", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_wr_wait", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_wr_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_reg_rd_addr", "type": "wire", "width": "[AXIL_CSR_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_reg_rd_en", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_rd_data", "type": "wire", "width": "[AXIL_CTRL_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_reg_rd_wait", "type": "wire", "width": "" }, { "direction": "out", "name": "ctrl_reg_rd_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "qsfp_tx_p", "type": "wire", "width": "[QSFP_CNT*4-1:0]" }, { "direction": "out", "name": "qsfp_tx_n", "type": "wire", "width": "[QSFP_CNT*4-1:0]" }, { "direction": "in", "name": "qsfp_rx_p", "type": "wire", "width": "[QSFP_CNT*4-1:0]" }, { "direction": "in", "name": "qsfp_rx_n", "type": "wire", "width": "[QSFP_CNT*4-1:0]" }, { "direction": "out", "name": "qsfp_modsell", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "out", "name": "qsfp_resetl", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "qsfp_modprsl", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "qsfp_intl", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "out", "name": "qsfp_lpmode", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "out", "name": "qsfp_gtpowergood", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "qsfp_mgt_refclk", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "in", "name": "qsfp_mgt_refclk_bufg", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "out", "name": "qsfp_rst", "type": "wire", "width": "[QSFP_CNT-1:0]" }, { "direction": "out", "name": "eth_tx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "eth_tx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_tx_ptp_ts_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_tx_ptp_ts_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_tx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "eth_tx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_rx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_ptp_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_ptp_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_ptp_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "eth_rx_ptp_ts_step", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "axis_eth_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "axis_eth_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "eth_rx_enable", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_status", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_en", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "eth_rx_lfc_req", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_lfc_ack", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "eth_rx_pfc_en", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "out", "name": "eth_rx_pfc_req", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "eth_rx_pfc_ack", "type": "wire", "width": "[PORT_COUNT*8-1:0]" }, { "direction": "in", "name": "i2c_scl_i", "type": "wire", "width": "" }, { "direction": "out", "name": "i2c_scl_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i2c_scl_t", "type": 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"type": "wire", "width": "" } ] } }, { "namespace": "analog-devices", "name": "ethernet_xcvu11p", "latest": "3dc381cf791c", "versions": [ "3dc381cf791c", "HEAD", "1336749ccfa9", "ca0618ef7b4f", "7b364c5dfd5e", "0.0.0" ], "description": "This file repackages Corundum MQNIC Core AXI with the sole purpose of providing it as an IP Core. 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"transmitter", "tx" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-13T08:20:05+00:00", "desc_source": "ports", "external_uses": [ { "library": "work", "package": "axi_ctrlif" }, { "library": "work", "package": "axi_streaming_dma_rx_fifo" }, { "library": "work", "package": "axi_streaming_dma_tx_fifo" }, { "library": "work", "package": "dma_fifo" }, { "library": "work", "package": "fifo_synchronizer" }, { "library": "work", "package": "i2s_clkgen" }, { "library": "work", "package": "i2s_controller" }, { "library": "work", "package": "i2s_rx" }, { "library": "work", "package": "i2s_tx" }, { "library": "work", "package": "pl330_dma_fifo" } ], "top_ports": { "i2s_tx": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "resetn", "type": "std_logic", "width": "" }, { "direction": "in", "name": "enable", "type": "Boolean", "width": "" }, { "direction": "in", "name": "bclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "channel_sync", "type": "std_logic", "width": "" }, { "direction": "in", "name": "frame_sync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sdata", "type": "std_logic_vector", "width": "C_NUM - 1 downto 0" }, { "direction": "out", "name": "ack", "type": "std_logic", "width": "" }, { "direction": "in", "name": "stb", "type": "std_logic", "width": "" }, { "direction": "in", "name": "data", "type": "std_logic_vector", "width": "C_SLOT_WIDTH-1 downto 0" } ] } }, { "namespace": "analog-devices", "name": "i3c_controller_bit_mod", "latest": "3dc381cf791c", "versions": [ "3dc381cf791c", "HEAD", "1336749ccfa9", "ca0618ef7b4f", "7b364c5dfd5e", "0.0.0" ], "description": "Modulates the SDA and SCL lanes. SCL high time is fixed at 40ns in I3C mode: * 4 clock cycles at 100MHz clk. * 2 clock cycles at 50MHz clk. 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"s_axis_ctrl_dma_write_desc_status_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_dma_addr", "type": "wire", "width": "[DMA_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_ram_sel", "type": "wire", "width": "[RAM_SEL_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_ram_addr", "type": "wire", "width": "[RAM_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_len", "type": "wire", "width": "[DMA_LEN_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_tag", "type": "wire", "width": "[DMA_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_read_desc_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_data_dma_read_desc_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_data_dma_read_desc_status_tag", "type": "wire", "width": "[DMA_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_data_dma_read_desc_status_error", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_axis_data_dma_read_desc_status_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_dma_addr", "type": "wire", "width": "[DMA_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_ram_sel", "type": "wire", "width": "[RAM_SEL_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_ram_addr", "type": "wire", "width": "[RAM_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_imm", "type": "wire", "width": "[DMA_IMM_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_imm_en", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_len", "type": "wire", "width": "[DMA_LEN_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_tag", "type": "wire", "width": "[DMA_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_data_dma_write_desc_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "m_axis_data_dma_write_desc_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axis_data_dma_write_desc_status_tag", "type": "wire", "width": "[DMA_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_data_dma_write_desc_status_error", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_axis_data_dma_write_desc_status_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl_dma_ram_wr_cmd_sel", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_wr_cmd_be", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_wr_cmd_addr", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_wr_cmd_data", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_wr_cmd_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "ctrl_dma_ram_wr_cmd_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "ctrl_dma_ram_wr_done", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_rd_cmd_sel", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_rd_cmd_addr", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_rd_cmd_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "ctrl_dma_ram_rd_cmd_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "ctrl_dma_ram_rd_resp_data", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "ctrl_dma_ram_rd_resp_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "ctrl_dma_ram_rd_resp_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "data_dma_ram_wr_cmd_sel", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_wr_cmd_be", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_wr_cmd_addr", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_wr_cmd_data", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_wr_cmd_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "data_dma_ram_wr_cmd_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "data_dma_ram_wr_done", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "data_dma_ram_rd_cmd_sel", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_rd_cmd_addr", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "data_dma_ram_rd_cmd_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "data_dma_ram_rd_cmd_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "out", "name": "data_dma_ram_rd_resp_data", "type": "wire", "width": "[RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "data_dma_ram_rd_resp_valid", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "data_dma_ram_rd_resp_ready", "type": "wire", "width": "[RAM_SEG_COUNT-1:0]" }, { "direction": "in", "name": "ptp_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sample_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_td_sd", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_locked", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_rel", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "ptp_sync_ts_rel_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_ts_tod", "type": "wire", "width": "[PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "ptp_sync_ts_tod_step", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_sync_pps_str", "type": "wire", "width": "" }, { "direction": "in", "name": "ptp_perout_locked", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_error", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "ptp_perout_pulse", "type": "wire", "width": "[PTP_PEROUT_COUNT-1:0]" }, { "direction": "in", "name": "direct_tx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "direct_tx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_direct_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_direct_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_TX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_cpl_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_cpl_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_tx_cpl_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_direct_tx_cpl_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_cpl_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_cpl_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_tx_cpl_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_direct_tx_cpl_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "direct_rx_clk", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "direct_rx_rst", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_direct_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_direct_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_direct_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_direct_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_direct_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_direct_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_direct_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_sync_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_sync_tx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_TX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_cpl_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_cpl_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_tx_cpl_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_sync_tx_cpl_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_cpl_ts", "type": "wire", "width": "[PORT_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_cpl_tag", "type": "wire", "width": "[PORT_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_tx_cpl_valid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_sync_tx_cpl_ready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_sync_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_sync_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_sync_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_sync_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_sync_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_rx_tdata", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_rx_tkeep", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_sync_rx_tvalid", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_sync_rx_tready", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_sync_rx_tlast", "type": "wire", "width": "[PORT_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_sync_rx_tuser", "type": "wire", "width": "[PORT_COUNT*AXIS_SYNC_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tdata", "type": "wire", "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tkeep", "type": "wire", "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tvalid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_if_tx_tready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tlast", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tid", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tdest", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_tuser", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tdata", "type": "wire", "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tkeep", "type": "wire", "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tvalid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_if_tx_tready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tlast", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tid", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tdest", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_tuser", "type": "wire", "width": "[IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_cpl_ts", "type": "wire", "width": "[IF_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_cpl_tag", "type": "wire", "width": "[IF_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_tx_cpl_valid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_if_tx_cpl_ready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_cpl_ts", "type": "wire", "width": "[IF_COUNT*PTP_TS_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_cpl_tag", "type": "wire", "width": "[IF_COUNT*TX_TAG_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_tx_cpl_valid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_if_tx_cpl_ready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tdata", "type": "wire", "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tkeep", "type": "wire", "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tvalid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "s_axis_if_rx_tready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tlast", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tid", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tdest", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0]" }, { "direction": "in", "name": "s_axis_if_rx_tuser", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tdata", "type": "wire", "width": "[IF_COUNT*AXIS_IF_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tkeep", "type": "wire", "width": "[IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tvalid", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "in", "name": "m_axis_if_rx_tready", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tlast", "type": "wire", "width": "[IF_COUNT-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tid", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tdest", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0]" }, { "direction": "out", "name": "m_axis_if_rx_tuser", "type": "wire", "width": "[IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0]" }, { "direction": "in", "name": "ddr_clk", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "in", "name": "ddr_rst", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awid", "type": "wire", "width": "[DDR_CH*AXI_DDR_ID_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awaddr", "type": "wire", "width": "[DDR_CH*AXI_DDR_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awlen", "type": "wire", "width": "[DDR_CH*8-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awsize", "type": "wire", "width": "[DDR_CH*3-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awburst", "type": "wire", "width": "[DDR_CH*2-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awlock", "type": "wire", "width": "[DDR_CH-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awcache", "type": "wire", "width": "[DDR_CH*4-1:0]" }, { "direction": "out", "name": "m_axi_ddr_awprot", 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"width": "" }, { "direction": "out", "name": "up_rx_pll_locked_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_0", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_0", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_0", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_0", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_0", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_0", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_0", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_0", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_0", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_0", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_0", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_0", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_0", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_0", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_0", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_0", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_0", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_0", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_0", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_0", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_0", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_0", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_1", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_1_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_1_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_1", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_1", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_1", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_1", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_1", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_1", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_1", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_1", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_1", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_1", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_1_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_1_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_1", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_1", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_1", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_1", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_1", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_1", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_1", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_1", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_1", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_1", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_1", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_1", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_1", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_1", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_1", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_1", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_2", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_2_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_2_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_2", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_2", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_2", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_2", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_2", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_2", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_2", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_2", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_2", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_2_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_2_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_2", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_2", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_2", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_2", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_2", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_2", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_2", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_2", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_2", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_2", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_2", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_2", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_2", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_2", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_2", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_2", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_3", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_3_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_3_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_3", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_3", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_3", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_3", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_3", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_3", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_3", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_3", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_3_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_3_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_3", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_3", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_3", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_3", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_3", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_3", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_3", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_3", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_3", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_3", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_3", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_3", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_3", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_3", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_3", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_3", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_3", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_4", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_4_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_4_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_4", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_4", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_4", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_4", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_4", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_4", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_4", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_4_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_4_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_4", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_4", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_4", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_4", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_4", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_4", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_4", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_4", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_4", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_4", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_4", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_4", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_4", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_4", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_5_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_5_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_5", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_5", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_5", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_5", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_5", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_5", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_5", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_5_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_5_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_5", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_5", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_5", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_5", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_5", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_5", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_5", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_5", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_5", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_5", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_5", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_5", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_5", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_5", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_5", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_5", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_6_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_6_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_6", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_6", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_6", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_6", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_6", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_6", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_6", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_6_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_6_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_6", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_6", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_6", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_6", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_6", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_6", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_6", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_6", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_6", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_6", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_6", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_6", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_6", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_6", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_6", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_6", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_7_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_7_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_7", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_7", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_7", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_7", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_7", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_7", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_7", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_7_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_7_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_7", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_7", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_7", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_7", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_7", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_7", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_7", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_7", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_7", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_7", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_7", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_7", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_7", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_7", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_7", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_7", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_8", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_8", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_8_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_8_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_8", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_8", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_8", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_8", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_8", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_8", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_8", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_8", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_8", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_8", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_8", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_8_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_8_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_8", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_8", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_8", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_8", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_8", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_8", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_8", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_8", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_8", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_8", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_8", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_8", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_8", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_8", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_8", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_8", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_8", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_9", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_9_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_9_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_9", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_9", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_9", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_9", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_9", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_9", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_9", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_9", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_9", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_9", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_9", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_9_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_9_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_9", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_9", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_9", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_9", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_9", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_9", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_9", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_9", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_9", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_9", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_9", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_9", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_9", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_9", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_9", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_9", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_9", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_9", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_9", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_10", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_10_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_10_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_10", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_10", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_10", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_10", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_10", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_10", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_10", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_10", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_10", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_10", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_10", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_10_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_10_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_10", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_10", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_10", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_10", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_10", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_10", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_10", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_10", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_10", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_10", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_10", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_10", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_10", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_10", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_10", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_10", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_10", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_10", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_10", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_11", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_11_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_11_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_11", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_11", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_11", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_11", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_11", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_11", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_11", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_11", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_11", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_11", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_11", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_11_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_11_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_11", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_11", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_11", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_11", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_11", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_11", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_11", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_11", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_11", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_11", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_11", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_11", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_11", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_11", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_11", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_11", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_11", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_11", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_11", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_12", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_12", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_12_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_12_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_12", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_12", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_12", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_12", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_12", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_12", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_12", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_12", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_12", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_12", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_12", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_12_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_12_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_12", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_12", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_12", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_12", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_12", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_12", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_12", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_12", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_12", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_12", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_12", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_12", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_12", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_12", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_12", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_12", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_12", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_13", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_13_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_13_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_13", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_13", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_13", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_13", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_13", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_13", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_13", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_13", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_13", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_13", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_13", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_13_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_13_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_13", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_13", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_13", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_13", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_13", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_13", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_13", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_13", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_13", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_13", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_13", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_13", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_13", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_13", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_13", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_13", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_13", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_13", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_13", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_14", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_14_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_14_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_14", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_14", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_14", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_14", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_14", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_14", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_14", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_14", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_14", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_14", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_14", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_14_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_14_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_14", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_14", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_14", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_14", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_14", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_14", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_14", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_14", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_14", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_14", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_14", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_14", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_14", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_14", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_14", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_14", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_14", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_14", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_14", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_15", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_15_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_15_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_15", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_15", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_15", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_15", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_15", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_15", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_15", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_15", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_15", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_15", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_15", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_15_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_15_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_15", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_15", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_15", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_15", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_15", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_15", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_15", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_15", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_15", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_15", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_15", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_15", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_15", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_15", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_15", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_15", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_15", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_15", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_15", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_16", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_16", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_16_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_16_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_16", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_16", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_16", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_16", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_16", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_16", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_16", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_16", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_16", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_16", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_16", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_16_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_16_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_16", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_16", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_16", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_16", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_16", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_16", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_16", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_16", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_16", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_16", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_16", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_16", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_16", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_16", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_16", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_16", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_16", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_17", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_17_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_17_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_17", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_17", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_17", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_17", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_17", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_17", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_17", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_17", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_17", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_17", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_17", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_17_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_17_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_17", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_17", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_17", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_17", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_17", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_17", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_17", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_17", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_17", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_17", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_17", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_17", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_17", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_17", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_17", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_17", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_17", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_17", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_17", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_18", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_18_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_18_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_18", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_18", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_18", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_18", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_18", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_18", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_18", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_18", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_18", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_18", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_18", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_18_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_18_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_18", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_18", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_18", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_18", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_18", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_18", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_18", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_18", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_18", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_18", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_18", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_18", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_18", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_18", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_18", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_18", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_18", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_18", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_18", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_19", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_19_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_19_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_19", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_19", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_19", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_19", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_19", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_19", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_19", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_19", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_19", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_19", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_19", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_19_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_19_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_19", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_19", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_19", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_19", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_19", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_19", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_19", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_19", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_19", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_19", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_19", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_19", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_19", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_19", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_19", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_19", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_19", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_19", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_19", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_20", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_20", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_20_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_20_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_20", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_20", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_20", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_20", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_20", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_20", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_20", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_20", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_20", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_20", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_20", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_20_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_20_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_20", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_20", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_20", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_20", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_20", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_20", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_20", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_20", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_20", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_20", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_20", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_20", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_20", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_20", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_20", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_20", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_20", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_21", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_21_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_21_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_21", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_21", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_21", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_21", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_21", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_21", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_21", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_21", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_21", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_21", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_21", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_21_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_21_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_21", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_21", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_21", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_21", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_21", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_21", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_21", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_21", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_21", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_21", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_21", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_21", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_21", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_21", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_21", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_21", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_21", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_21", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_21", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_22", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_22_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_22_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_22", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_22", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_22", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_22", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_22", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_22", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_22", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_22", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_22", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_22", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_22", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_22_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_22_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_22", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_22", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_22", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_22", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_22", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_22", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_22", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_22", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_22", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_22", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_22", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_22", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_22", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_22", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_22", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_22", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_22", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_22", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_22", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_23", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_23_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_23_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_23", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_23", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_23", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_23", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_23", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_23", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_23", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_23", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_23", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_23", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_23", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_23_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_23_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_23", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_23", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_23", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_23", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_23", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_23", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_23", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_23", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_23", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_23", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_23", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_23", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_23", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_23", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_23", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_23", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_23", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_23", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_23", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_24", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_24", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_24_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_24_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_24", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_24", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_24", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_24", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_24", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_24", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_24", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_24", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_24", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_24", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_24", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_24_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_24_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_24", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_24", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_24", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_24", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_24", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_24", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_24", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_24", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_24", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_24", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_24", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_24", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_24", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_24", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_24", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_24", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_24", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_25", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_25_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_25_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_25", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_25", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_25", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_25", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_25", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_25", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_25", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_25", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_25", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_25", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_25", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_25_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_25_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_25", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_25", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_25", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_25", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_25", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_25", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_25", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_25", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_25", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_25", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_25", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_25", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_25", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_25", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_25", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_25", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_25", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_25", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_25", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_26", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_26_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_26_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_26", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_26", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_26", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_26", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_26", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_26", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_26", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_26", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_26", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_26", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_26", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_26_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_26_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_26", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_26", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_26", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_26", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_26", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_26", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_26", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_26", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_26", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_26", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_26", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_26", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_26", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_26", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_26", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_26", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_26", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_26", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_26", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_27", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_27_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_27_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_27", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_27", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_27", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_27", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_27", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_27", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_27", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_27", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_27", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_27", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_27", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_27_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_27_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_27", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_27", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_27", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_27", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_27", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_27", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_27", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_27", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_27", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_27", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_27", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_27", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_27", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_27", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_27", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_27", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_27", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_27", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_27", "type": "wire", "width": "" }, { "direction": "in", "name": "qpll_ref_clk_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_qpll_rst_28", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_28", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_28_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_28_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_28", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_28", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_28", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_28", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_28", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_28", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_28", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_28", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_28", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_28", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_28", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_28_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_28_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_28", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_28", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_28", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_28", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_28", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_28", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_28", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_cm_enb_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_addr_28", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_cm_wr_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cm_wdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_rdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_cm_ready_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_enb_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_28", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_28", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_28", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_28", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_28", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_28", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_28", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_28", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_28", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_28", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_28", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_28", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_28", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_28", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_28", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_28", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_28", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_28", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_rdata_28", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_tx_ready_28", "type": "wire", "width": "" }, { "direction": "in", "name": "cpll_ref_clk_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_cpll_rst_29", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_29_p", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_29_n", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_29", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_out_clk_div2_29", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_29", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_clk_2x_29", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_charisk_29", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_disperr_29", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_notintable_29", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "out", "name": "rx_data_29", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "rx_calign_29", "type": "wire", "width": "" }, { "direction": "out", "name": "rx_header_29", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rx_block_sync_29", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_29_p", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_29_n", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_29", "type": "wire", "width": "" }, { "direction": "out", "name": "tx_out_clk_div2_29", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_29", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_clk_2x_29", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_charisk_29", "type": "wire", "width": "[DATA_PATH_WIDTH-1:0]" }, { "direction": "in", "name": "tx_data_29", "type": "wire", "width": "[DATA_PATH_WIDTH*8-1:0]" }, { "direction": "in", "name": "tx_header_29", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "up_es_enb_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_addr_29", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_es_wr_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_wdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_rdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_es_ready_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_es_reset_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_pll_locked_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rst_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_user_ready_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_rst_done_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_prbssel_29", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_rx_prbscntreset_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbserr_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_prbslocked_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_rx_bufstatus_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_bufstatus_rst_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_lpm_dfe_n_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_rate_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_sys_clk_sel_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_rx_out_clk_sel_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_rx_enb_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_addr_29", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_rx_wr_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_rx_wdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_rdata_29", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "up_rx_ready_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_pll_locked_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rst_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_user_ready_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_rst_done_29", "type": "wire", "width": "" }, { "direction": "out", "name": "up_tx_bufstatus_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_prbsforceerr_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_prbssel_29", "type": "wire", "width": "[ 3:0]" }, { "direction": "in", "name": "up_tx_lpm_dfe_n_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_rate_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_sys_clk_sel_29", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "up_tx_out_clk_sel_29", "type": "wire", "width": "[ 2:0]" }, { "direction": "in", "name": "up_tx_diffctrl_29", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_postcursor_29", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_precursor_29", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "up_tx_enb_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_addr_29", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "up_tx_wr_29", "type": "wire", "width": "" }, { "direction": "in", "name": "up_tx_wdata_29", "type": "wire", "width": "[15:0]" }, { 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"type": "wire", "width": "" }, { "direction": "out", "name": "bios_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_csn", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_wrn", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_hld", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_wdat", "type": "wire", "width": "" }, { "direction": "in", "name": "pll_xbuf", "type": "wire", "width": "" }, { "direction": "in", "name": "pll_xbuf1", "type": "wire", "width": "" }, { "direction": "inout", "name": "pll_sclk", "type": "wire", "width": "" }, { "direction": "inout", "name": "pll_sdat", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_dclk", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_hsync", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_vsync", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_de", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_data", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "dvo_bsel_scl", "type": "wire", "width": "" }, { "direction": "inout", "name": "dvo_dsel_sda", "type": "wire", "width": "" }, { "direction": "inout", "name": "ddc_scl", "type": "wire", "width": "" }, { "direction": "inout", "name": "ddc_sda", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_psaven", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_cblankn", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_csyncn", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_sog", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_clko", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_clki", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_field", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_hsyncn", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_vsyncn", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_blankn", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_pal", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_clk_sel", "type": "wire", "width": "" }, { "direction": "in", "name": "mb_32_sel", "type": "wire", "width": "" }, { "direction": "in", "name": "vga_en", "type": "wire", "width": "" }, { "direction": "in", "name": "dual_enn", "type": "wire", "width": "" }, { "direction": "in", "name": "m66_en", "type": "wire", "width": "" }, { "direction": "out", "name": "ledn", "type": "wire", "width": "" }, { "direction": "in", "name": "mictor_clke", "type": "wire", "width": "" }, { "direction": "in", "name": "mictor_clko", "type": "wire", "width": "" }, { "direction": "in", "name": "mictor_de", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "mictor_do", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "gpio_3v", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "mem_odt", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cs_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cke", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_addr", "type": "wire", "width": "[13:0]" }, { "direction": "out", "name": "mem_ba", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "mem_ras_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cas_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_we_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_dm", "type": "wire", "width": "[BYTES/4-1:0]" }, { "direction": "inout", "name": "mem_clk", "type": "wire", "width": "" }, { "direction": "inout", "name": "mem_clk_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_reset_n", "type": "wire", "width": "" }, { "direction": "inout", "name": "mem_dq", "type": "wire", "width": "[31:0]" }, { "direction": "inout", "name": "mem_dqs", "type": "wire", "width": "[3:0]" }, { "direction": "inout", "name": "mem_dqsn", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "pll_25_37p5", "type": "wire", "width": "" } ], "max_3d_top": [ { "direction": "in", "name": "hclock", "type": "wire", "width": "" }, { "direction": "in", "name": "port", "type": "wire", "width": "" }, { "direction": "in", "name": "hresetn", "type": "wire", "width": "" }, { "direction": "inout", "name": "pframen", "type": "wire", "width": "" }, { "direction": "inout", "name": "pirdyn", "type": "wire", "width": "" }, { "direction": "inout", "name": "ptrdyn", "type": "wire", "width": "" }, { "direction": "inout", "name": "pdevseln", "type": "wire", "width": "" }, { "direction": "in", "name": "pidsel", "type": "wire", "width": "" }, { "direction": "inout", "name": "pintan", "type": "wire", "width": "" }, { "direction": "out", "name": "inout", "type": "wire", "width": "" }, { "direction": "inout", "name": "pgnntn", "type": "wire", "width": "" }, { "direction": "inout", "name": "pcben", "type": "wire", "width": "[3:0]" }, { "direction": "inout", "name": "pad", "type": "wire", "width": "[31:00]" }, { "direction": "in", "name": "bios_rdat", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_csn", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_wrn", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_hld", "type": "wire", "width": "" }, { "direction": "out", "name": "bios_wdat", "type": "wire", "width": "" }, { "direction": "in", "name": "pll_clka", "type": "wire", "width": "" }, { "direction": "in", "name": "pll_clkb", "type": "wire", "width": "" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "inout", "name": "pll_sclk", "type": "wire", "width": "" }, { "direction": "inout", "name": "pll_sdat", "type": "wire", "width": "" }, { "direction": "inout", "name": "mem_clk", "type": "wire", "width": "" }, { "direction": "inout", "name": "mem_clk_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cke", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cs_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_odt", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_ras_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_cas_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_we_n", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_ba", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "mem_addr", "type": "wire", "width": "[13:0]" }, { "direction": "inout", "name": "mem_dq", "type": "wire", "width": "[63:0]" }, { "direction": "inout", "name": "mem_dqs", "type": "wire", "width": "[7:0]" }, { "direction": "inout", "name": "mem_dqsn", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "mem_dm", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "dvo_dclk", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_hsync", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_vsync", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_de", "type": "wire", "width": "" }, { "direction": "out", "name": "dvo_data", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "dvo_bsel_scl", "type": "wire", "width": "" }, { "direction": "inout", "name": "dvo_dsel_sda", "type": "wire", "width": "" }, { "direction": "inout", "name": "ddc_scl", "type": "wire", "width": "" }, { "direction": "inout", "name": "ddc_sda", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_psaven", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_cblankn", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_csyncn", "type": "wire", "width": "" }, { "direction": "out", "name": "dac_sog", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_clko", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_hsyncn", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_vsyncn", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_blankn", "type": "wire", "width": "" }, { "direction": "in", "name": "bt_field", "type": "wire", "width": "" }, { "direction": "out", "name": "bt_pal", "type": "wire", "width": "" }, { "direction": "in", "name": "t2r4_mode", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "mb_32_sel", "type": "wire", "width": "" }, { "direction": "in", "name": "vga_en", "type": "wire", "width": "" }, { "direction": "in", "name": "dual_enn", "type": "wire", "width": "" }, { "direction": "in", "name": "m66_en", "type": "wire", "width": "" }, { "direction": "out", "name": "ledn", "type": "wire", "width": "" }, { "direction": "out", "name": "mictor_clke", "type": "wire", "width": "" }, { "direction": "out", "name": "mictor_clko", "type": "wire", "width": "" }, { "direction": "out", "name": "mictor_de", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "mictor_do", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "gpio_3v", "type": "wire", "width": "[19:0]" } ], "ram_tag": [ { "direction": "in", "name": "de_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "de_rstn", "type": "wire", "width": "" }, { "direction": "in", "name": "cur_mipmap", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ee_s0_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "ee_s1_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "eo_s0_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "eo_s1_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "oe_s0_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "oe_s1_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "oo_s0_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "oo_s1_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "ee_tag_adr_rd", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "eo_tag_adr_rd", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "oe_tag_adr_rd", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "oo_tag_adr_rd", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ee_tag_adr_wr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "eo_tag_adr_wr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "oe_tag_adr_wr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "oo_tag_adr_wr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ee_tag_dat_in", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "eo_tag_dat_in", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "oe_tag_dat_in", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "oo_tag_dat_in", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "tag_ram_csn", "type": "wire", "width": "" }, { "direction": "out", "name": "ee_tag_dat_out", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "eo_tag_dat_out", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "oe_tag_dat_out", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "oo_tag_dat_out", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "tag_s0_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "tag_s1_loadn", "type": "wire", "width": "" }, { "direction": "in", "name": "tag_adr_wr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "tag_adr_rd", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "tag_dat_in", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "tag_dat_out", "type": "wire", "width": "[23:0]" } ], "sm_ref": [ { "direction": "in", "name": "mem_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "hreset_n", "type": "wire", "width": "" }, { "direction": "in", "name": "ref_gnt", "type": "wire", "width": "" }, { "direction": "in", "name": "svga_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "c_cr11_b6", "type": "wire", "width": "" }, { "direction": "in", "name": "sync_c_crt_line_end", "type": "wire", "width": "" }, { "direction": "out", "name": "ref_svga_req", "type": "wire", "width": "" }, { "direction": "out", "name": "ref_req", "type": "wire", "width": "" }, { "direction": "out", "name": "m_t_ref_n", "type": "wire", "width": "" }, { "direction": "out", "name": "ref_cycle_done", "type": "wire", "width": "" } ] }, "top_modules": [ "de3d_fog_table", "de3d_read_addr_in", "de3d_tfog", "des_comp_gen_fx", "fifo_267x128", "flt2int", "flt_frac_test", "flt_fx_mult", "flt_fx_rnd", "flt_fx_uv", "flt_recip_iter", "flt_recip_rom", "graph_core", "max_3d_top", "ram_tag", "sm_ref", "sv_log2" ] }, { "namespace": "catalyst-neuromorphic", "name": "catalyst-n2", "latest": "583f9e012f66", "versions": [ "583f9e012f66", "HEAD" ], "description": "Open-source neuromorphic processor (second generation) \u2014 LIF compartmental neurons, microcode learning, STDP + three-factor synaptic plasticity, asynchronous Network-on-Chip mesh, RV32I/RV32IM management cores, multi-chip routing. Apache-2.0, FPGA-validated on AWS F2, Kria, and Arty.", "license": "Apache-2.0", "language": "verilog", "library": "work", "source_url": "https://github.com/catalyst-neuromorphic/catalyst-n2.git", "tags": [ "adapter", "asynchronous", "cluster", "converter", "interface", "neuromorphic", "protocol", "receiver", "scalable", "transmit", "transmitter", "universal" ], "role": "top", "library_deps": [], "created_at": "2026-05-07T05:42:39Z", "updated_at": "2026-03-20T17:34:38+00:00", "desc_source": "verdict", "top_ports": { "axi_uart_bridge": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_neuro", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_neuro_n", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axi_awaddr", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_axi_awvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axi_awready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axi_wdata", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_axi_wstrb", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "s_axi_wvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axi_wready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axi_bresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axi_bvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axi_bready", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axi_araddr", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s_axi_arvalid", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axi_arready", "type": "wire", "width": "" }, { "direction": "out", "name": "s_axi_rdata", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "s_axi_rresp", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "s_axi_rvalid", "type": "wire", "width": "" }, { "direction": "in", "name": "s_axi_rready", "type": "wire", "width": "" }, { "direction": "out", "name": "hi_rx_data", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "hi_rx_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "hi_tx_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "hi_tx_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "hi_tx_ready", "type": "wire", "width": "" } ], "multi_chip_router": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "my_chip_id", "type": "wire", "width": "[CHIP_ID_BITS-1:0]" }, { "direction": "in", "name": "tx_push", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_dest_chip", "type": "wire", "width": "[CHIP_ID_BITS-1:0]" }, { "direction": "in", "name": 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"width": "" } ], "taxi_axil_tie": [ { "direction": "wr_slv", "name": "s_axil_wr", "type": "taxi_axil_if.wr_slv", "width": "" }, { "direction": "rd_slv", "name": "s_axil_rd", "type": "taxi_axil_if.rd_slv", "width": "" }, { "direction": "wr_mst", "name": "m_axil_wr", "type": "taxi_axil_if.wr_mst", "width": "" }, { "direction": "rd_mst", "name": "m_axil_rd", "type": "taxi_axil_if.rd_mst", "width": "" } ] }, "top_modules": [ "taxi_apb_adapter", "taxi_apb_axil_adapter", "taxi_apb_dp_ram", "taxi_apb_interconnect", "taxi_apb_interconnect_1s", "taxi_apb_ram", "taxi_apb_tie", "taxi_axi_adapter", "taxi_axi_axil_adapter", "taxi_axi_cdma", "taxi_axi_crossbar", "taxi_axi_crossbar_1s", "taxi_axi_dma", "taxi_axi_dp_ram", "taxi_axi_fifo", "taxi_axi_interconnect", "taxi_axi_interconnect_1s", "taxi_axi_ram", "taxi_axi_register", "taxi_axi_tie", "taxi_axil_adapter", "taxi_axil_apb_adapter", "taxi_axil_axi_adapter", "taxi_axil_crossbar", "taxi_axil_crossbar_1s", "taxi_axil_dp_ram", "taxi_axil_interconnect", "taxi_axil_interconnect_1s", "taxi_axil_ram", "taxi_axil_register", "taxi_axil_tie" ] }, { "namespace": "fpganinja", "name": "taxi-axis", "latest": "master", "versions": [ "master" ], "description": "AXI4-Stream infrastructure: FIFOs (sync/async/pipeline), broadcast, demux/mux, switch, register, COBS encode/decode, null src/snk, tie. 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"direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_async_fifo_adapter": [ { "direction": "out", "name": "FIFO", "type": "wire", "width": "" }, { "direction": "in", "name": "parameter", "type": "wire", "width": "" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "bus", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_broadcast": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "in", "name": "next", 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"direction": "in", "name": "in", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_concat": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "empty", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_demux": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "empty", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_fifo_adapter": [ { "direction": "out", "name": "FIFO", "type": "wire", "width": "" }, { "direction": "in", "name": "parameter", "type": "wire", "width": "" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "bus", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_mux": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "in", "name": "next", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "empty", "type": "wire", "width": "" }, { "direction": "out", "name": "m_axis_tvalid_next", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "" }, { "direction": "snk", "name": "s_axis", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "src", "name": "m_axis", "type": "taxi_axis_if.src", "width": "" } ], "taxi_axis_null_snk": [ { "direction": "snk", "name": "s_axis", "type": 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"type": "taxi_dma_desc_if.sts_src", "width": "" }, { "direction": "snk", "name": "s_axis_wr_data", "type": "taxi_axis_if.snk", "width": "" }, { "direction": "wr_mst", "name": "dma_ram_wr", "type": "taxi_dma_ram_if.wr_mst", "width": "" } ], "taxi_dma_client_axis_source": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "datapath", "type": "wire", "width": "" }, { "direction": "req_snk", "name": "desc_req", "type": "taxi_dma_desc_if.req_snk", "width": "" }, { "direction": "sts_src", "name": "desc_sts", "type": "taxi_dma_desc_if.sts_src", "width": "" }, { "direction": "src", "name": "m_axis_rd_data", "type": "taxi_axis_if.src", "width": "" }, { "direction": "rd_mst", "name": "dma_ram_rd", "type": "taxi_dma_ram_if.rd_mst", "width": "" } ], "taxi_dma_if_axi": [ { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "wr_mst", "name": "m_axi_wr", "type": "taxi_axi_if.wr_mst", "width": "" }, { "direction": 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"name": "ctrl_i", "type": "ctrl_bus_t", "width": "" }, { "direction": "in", "name": "csr_we_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "csr_addr_i", "type": "std_ulogic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "csr_wdata_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "csr_rdata_o", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "equal_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "less_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rs1_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "rs2_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "res_o", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "valid_o", "type": "std_ulogic", "width": "" } ], "neorv32_cpu_frontend_ipb": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "ctrl_i", "type": "ctrl_bus_t", "width": "" }, { "direction": "out", "name": "ibus_req_o", "type": "bus_req_t", "width": "" }, { "direction": "in", "name": "ibus_rsp_i", "type": "bus_rsp_t", "width": "" }, { "direction": "out", "name": "pmp_addr_o", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "pmp_priv_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "pmp_err_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "frontend_o", "type": "if_bus_t", "width": "" } ], "neorv32_cpu_trace_simlog": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "ctrl_i", "type": "ctrl_bus_t", "width": "" }, { "direction": "in", "name": "rs1_rdata_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "rs2_rdata_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "rd_wdata_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "mem_ben_i", "type": "std_ulogic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "mem_addr_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "mem_wdata_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "trace_o", "type": "trace_port_t", "width": "" } ], "neorv32_gptmr_slice": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "bus_req_i", "type": "bus_req_t", "width": "" }, { "direction": "out", "name": "bus_rsp_o", "type": "bus_rsp_t", "width": "" }, { "direction": "in", "name": "clkgen_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "irq_o", "type": "std_ulogic", "width": "" } ], "neorv32_litex_core_complex": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tck_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tdi_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "jtag_tdo_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tms_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_adr_o", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_ulogic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_we_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_sel_o", "type": "std_ulogic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "wb_stb_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_cyc_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_ack_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_err_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "irq_mei_i", "type": "std_ulogic", "width": "" } ], "neorv32_prim_fifo": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "clear_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wdata_i", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "free_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "re_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "rdata_o", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "out", "name": "avail_o", "type": "std_ulogic", "width": "" } ], "neorv32_prim_mul": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "clear_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wdata_i", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "free_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "re_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "rdata_o", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "out", "name": "avail_o", "type": "std_ulogic", "width": "" } ], "neorv32_prim_spram": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "clear_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wdata_i", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "free_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "re_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "rdata_o", "type": "std_ulogic_vector", "width": "DWIDTH-1 downto 0" }, { "direction": "out", "name": "avail_o", "type": "std_ulogic", "width": "" } ], "neorv32_pwm_channel": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "bus_req_i", "type": "bus_req_t", "width": "" }, { "direction": "out", "name": "bus_rsp_o", "type": "bus_rsp_t", "width": "" }, { "direction": "in", "name": "clkgen_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "pwm_o", "type": "std_ulogic_vector", "width": "31 downto 0" } ], "neorv32_sys_reset": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_ext_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_wdt_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_dbg_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "rstn_ext_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "rstn_sys_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "xrstn_wdt_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "xrstn_ocd_o", "type": "std_ulogic", "width": "" } ], "neorv32_test_setup_approm": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_ulogic_vector", "width": "7 downto 0" } ], "neorv32_test_setup_bootloader": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "uart0_txd_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "uart0_rxd_i", "type": "std_ulogic", "width": "" } ], "neorv32_test_setup_on_chip_debugger": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tck_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tdi_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "jtag_tdo_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "jtag_tms_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "uart0_txd_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "uart0_rxd_i", "type": "std_ulogic", "width": "" } ], "neorv32_trng": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "bus_req_i", "type": "bus_req_t", "width": "" }, { "direction": "out", "name": "bus_rsp_o", "type": "bus_rsp_t", "width": "" }, { "direction": "out", "name": "irq_o", "type": "std_ulogic", "width": "" } ], "neorv32_verilog_wrapper": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "uart0_txd_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "uart0_rxd_i", "type": "std_ulogic", "width": "" } ], "neorv32_vivado_ip": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "resetn", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ocd_resetn", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wdt_resetn", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_awaddr", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_awlen", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "m_axi_awsize", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "m_axi_awburst", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "m_axi_awcache", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "m_axi_awprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "m_axi_awvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_awready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_wdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_wstrb", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "m_axi_wlast", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_wvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_wready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_araddr", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_arlen", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "m_axi_arsize", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "m_axi_arburst", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "m_axi_arcache", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "m_axi_arprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "m_axi_arvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_arready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_rdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "m_axi_rresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "m_axi_rlast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_rvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_rready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_bresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "m_axi_bvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_bready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s0_axis_tdest", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "s0_axis_tvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s0_axis_tready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s0_axis_tdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "s0_axis_tlast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s1_axis_tid", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "s1_axis_tvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s1_axis_tready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s1_axis_tdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "s1_axis_tlast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "jtag_tck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "jtag_tdi_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "jtag_tdo_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "jtag_tms_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "gpio_dir_o", "type": "std_logic_vector", "width": "IO_GPIO_DIR_NUM-1 downto 0" }, { "direction": "out", "name": "gpio_o", "type": "std_logic_vector", "width": "IO_GPIO_OUT_NUM-1 downto 0" }, { "direction": "in", "name": "gpio_i", "type": "std_logic_vector", "width": "IO_GPIO_IN_NUM-1 downto 0" }, { "direction": "out", "name": "uart0_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart0_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "uart0_rtsn_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart0_ctsn_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "uart1_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart1_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "uart1_rtsn_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart1_ctsn_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_clk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_dat_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_dat_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_csn_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "sdi_clk_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sdi_dat_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sdi_dat_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sdi_csn_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "twi_sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "twi_sda_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "twi_scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "twi_scl_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "twd_sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "twd_sda_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "twd_scl_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "onewire_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "onewire_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pwm_o", "type": "std_logic_vector", "width": "IO_PWM_NUM-1 downto 0" }, { "direction": "in", "name": "cfs_in_i", "type": "std_logic_vector", "width": "255 downto 0" }, { "direction": "out", "name": "cfs_out_o", "type": "std_logic_vector", "width": "255 downto 0" }, { "direction": "out", "name": "neoled_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "mtime_time_o", "type": "std_logic_vector", "width": "63 downto 0" }, { "direction": "in", "name": "irq_msi_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "irq_mti_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "irq_mei_i", "type": "std_logic", "width": "" } ] }, "top_modules": [ "neoTRNG_cell", "neorv32_bus_amo_rvs", "neorv32_bus_gateway", "neorv32_bus_io_switch", "neorv32_bus_reg", "neorv32_bus_switch", "neorv32_clint_mtimecmp", "neorv32_cpu_alu_fpu_f2i", "neorv32_cpu_alu_fpu_normalizer", "neorv32_cpu_frontend_ipb", "neorv32_cpu_trace_simlog", "neorv32_gptmr_slice", "neorv32_litex_core_complex", "neorv32_prim_fifo", "neorv32_prim_mul", "neorv32_prim_spram", "neorv32_pwm_channel", "neorv32_sys_reset", "neorv32_test_setup_approm", "neorv32_test_setup_bootloader", "neorv32_test_setup_on_chip_debugger", "neorv32_trng", "neorv32_verilog_wrapper", "neorv32_vivado_ip" ] }, { "namespace": "ohwr", "name": "etherbone-core", "latest": "master", "versions": [ "master" ], "description": "Etherbone \u2014 Wishbone-over-Ethernet remote-access protocol. Three HDL subsystems: Etherbone master (eb_master_core), slave (eb_slave_core, used by White Rabbit's wrc_core for remote register access), and a USB transport variant (eb_usb_core). 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Edge detectors, CDC synchronizers (gc_sync_*), pulse synchronizer, debouncers, Wishbone primitives + slaves + crossbars (wb_*/xwb_*), generic memory primitives (genram_pkg single/dual-port + async FIFO), AXI/DSP/I2C primitives, 8b/10b coder, radiation-tolerant variants. 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"width": "" }, { "direction": "in", "name": "m_bresp", "type": "STD_LOGIC_VECTOR", "width": "1 downto 0" }, { "direction": "in", "name": "m_bvalid", "type": "STD_LOGIC", "width": "" }, { "direction": "out", "name": "m_bready", "type": "STD_LOGIC", "width": "" }, { "direction": "out", "name": "m_araddr", "type": "STD_LOGIC_VECTOR", "width": "g_ADDR_WIDTH - 1 downto 0" }, { "direction": "out", "name": "m_arvalid", "type": "STD_LOGIC", "width": "" }, { "direction": "in", "name": "m_arready", "type": "STD_LOGIC", "width": "" }, { "direction": "in", "name": "m_rdata", "type": "STD_LOGIC_VECTOR", "width": "g_DATA_WIDTH - 1 downto 0" }, { "direction": "in", "name": "m_rresp", "type": "STD_LOGIC_VECTOR", "width": "1 downto 0" }, { "direction": "in", "name": "m_rvalid", "type": "STD_LOGIC", "width": "" }, { "direction": "out", "name": "m_rready", "type": "STD_LOGIC", "width": "" } ], "axi4lite_i2c_master": [ { "direction": "in", "name": "s_axi_aclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_aresetn", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_awaddr", "type": "std_logic_vector", "width": "C_S_AXI_ADDR_WIDTH-1 downto 0" }, { "direction": "in", "name": "s_axi_awprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "s_axi_awvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s_axi_awready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_wdata", "type": "std_logic_vector", "width": "C_S_AXI_DATA_WIDTH-1 downto 0" }, { "direction": "in", "name": "s_axi_wstrb", "type": "std_logic_vector", "width": "(C_S_AXI_DATA_WIDTH/8)-1 downto 0" }, { "direction": "in", "name": "s_axi_wvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s_axi_wready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s_axi_bresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "s_axi_bvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_bready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_araddr", "type": "std_logic_vector", "width": "C_S_AXI_ADDR_WIDTH-1 downto 0" }, { "direction": "in", "name": "s_axi_arprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "s_axi_arvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s_axi_arready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "s_axi_rdata", "type": "std_logic_vector", "width": "C_S_AXI_DATA_WIDTH-1 downto 0" }, { "direction": "out", "name": "s_axi_rresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "s_axi_rvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_axi_rready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2c_scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2c_scl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2c_scl_t", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2c_sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2c_sda_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2c_sda_t", "type": "std_logic", "width": "" }, { "direction": "out", "name": "irq_o", "type": "std_logic", "width": "" } ], "axi_gpio_expander": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "error_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "gpio_out", "type": "std_logic_vector", "width": "g_num-1 downto 0" }, { "direction": "in", "name": "gpio_oe", "type": "std_logic_vector", "width": "g_num-1 downto 0" }, { "direction": "in", "name": "gpio_dir", "type": "std_logic_vector", "width": "g_num-1 downto 0" }, { "direction": "out", "name": "gpio_in", "type": "std_logic_vector", "width": "g_num-1 downto 0" }, { "direction": "out", "name": "ARVALID", "type": "std_logic", "width": "" }, { "direction": "out", "name": "AWVALID", "type": "std_logic", "width": "" }, { "direction": "out", "name": "BREADY", "type": "std_logic", "width": "" }, { "direction": "out", "name": "RREADY", "type": "std_logic", "width": "" }, { "direction": "out", "name": "WVALID", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ARADDR", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "AWADDR", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "WDATA", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "WSTRB", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "ARREADY", "type": "std_logic", "width": "" }, { "direction": "in", "name": "AWREADY", "type": "std_logic", "width": "" }, { "direction": "in", "name": "BVALID", "type": "std_logic", "width": "" }, { "direction": "in", "name": "RLAST", "type": "std_logic", "width": "" }, { "direction": "in", "name": "RVALID", "type": "std_logic", "width": "" }, { "direction": "in", "name": "WREADY", "type": "std_logic", "width": "" }, { "direction": "in", "name": "BRESP", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "RRESP", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "RDATA", "type": "std_logic_vector", "width": "31 downto 0" } ], "cheby_dpssram": [ { "direction": "in", "name": "clk_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "addr_a_i", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "addr_b_i", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "data_a_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "data_b_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "data_a_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "data_b_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "bwsel_a_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "bwsel_b_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "rd_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rd_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_b_i", "type": "std_logic", "width": "" } ], "dec_8b10b_ctrl": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_10b_i", "type": "std_logic_vector", "width": "9 downto 0" }, { "direction": "out", "name": "ctrl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "code_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rdisp_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_8b_o", "type": "std_logic_vector", "width": "7 downto 0" } ], "dec_8b10b_disp": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_10b_i", "type": "std_logic_vector", "width": "9 downto 0" }, { "direction": "out", "name": "ctrl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "code_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rdisp_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_8b_o", "type": "std_logic_vector", "width": "7 downto 0" } ], "dec_8b10b_lut": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_10b_i", "type": "std_logic_vector", "width": "9 downto 0" }, { "direction": "out", "name": "ctrl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "code_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rdisp_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_8b_o", "type": "std_logic_vector", "width": "7 downto 0" } ], "flash_top": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rstn_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "clk_ext_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_out_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic", "width": "" } ], "gc_arbitrated_mux": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_num_inputs * g_width-1 downto 0" }, { "direction": "in", "name": "d_valid_i", "type": "std_logic_vector", "width": "g_num_inputs-1 downto 0" }, { "direction": "out", "name": "d_req_o", "type": "std_logic_vector", "width": "g_num_inputs-1 downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_width-1 downto 0" }, { "direction": "out", "name": "q_valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_input_id_o", "type": "std_logic_vector", "width": "f_log2_ceil(g_num_inputs)-1 downto 0" } ], "gc_argb_led_drv": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "g_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "r_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "b_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "valid_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dout_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ready_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "res_o", "type": "std_logic", "width": "" } ], "gc_async_counter_diff": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_inc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_dec_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "inc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dec_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "counter_o", "type": "std_logic_vector", "width": "g_bits downto 0" } ], "gc_async_signals_input_stage": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "signals_a_i", "type": "std_logic_vector", "width": "g_signal_num-1 downto 0" }, { "direction": "in", "name": "config_active_i", "type": "std_logic_vector", "width": "g_signal_num-1 downto 0" }, { "direction": "out", "name": "signals_o", "type": "std_logic_vector", "width": "g_signal_num-1 downto 0" }, { "direction": "out", "name": "signals_p1_o", "type": "std_logic_vector", "width": "g_signal_num-1 downto 0" }, { "direction": "out", "name": "signals_pN_o", "type": "std_logic_vector", "width": "g_signal_num-1 downto 0" } ], "gc_bicolor_led_ctrl": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "led_intensity_i", "type": "std_logic_vector", "width": "6 downto 0" }, { "direction": "in", "name": "led_state_i", "type": "std_logic_vector", "width": "(g_nb_line * g_nb_column * 2) - 1 downto 0" }, { "direction": "out", "name": "column_o", "type": "std_logic_vector", "width": "g_nb_column - 1 downto 0" }, { "direction": "out", "name": "line_o", "type": "std_logic_vector", "width": "g_nb_line - 1 downto 0" }, { "direction": "out", "name": "line_oen_o", "type": "std_logic_vector", "width": "g_nb_line - 1 downto 0" } ], "gc_cic": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ratio_sel_i", "type": "std_logic_vector", "width": "g_RATIO_SEL_WIDTH-1 downto 0" }, { "direction": "out", "name": "ratio_changed_o", "type": "std_logic", "width": "" } ], "gc_cic_combs": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ratio_sel_i", "type": "std_logic_vector", "width": "g_RATIO_SEL_WIDTH-1 downto 0" }, { "direction": "out", "name": "ratio_changed_o", "type": "std_logic", "width": "" } ], "gc_cic_decimator": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ratio_sel_i", "type": "std_logic_vector", "width": "g_RATIO_SEL_WIDTH-1 downto 0" }, { "direction": "out", "name": "ratio_changed_o", "type": "std_logic", "width": "" } ], "gc_cic_integrators": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ratio_sel_i", "type": "std_logic_vector", "width": "g_RATIO_SEL_WIDTH-1 downto 0" }, { "direction": "out", "name": "ratio_changed_o", "type": "std_logic", "width": "" } ], "gc_cic_ratio_change_detect": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ratio_sel_i", "type": "std_logic_vector", "width": "g_RATIO_SEL_WIDTH-1 downto 0" }, { "direction": "out", "name": "ratio_changed_o", "type": "std_logic", "width": "" } ], "gc_comparator": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pol_inv_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "enable_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "inp_i", "type": "std_logic_vector", "width": "g_IN_WIDTH-1 downto 0" }, { "direction": "in", "name": "inn_i", "type": "std_logic_vector", "width": "g_IN_WIDTH-1 downto 0" }, { "direction": "in", "name": "hys_i", "type": "std_logic_vector", "width": "g_IN_WIDTH-1 downto 0" }, { "direction": "out", "name": "out_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_p_o", "type": "std_logic", "width": "" } ], "gc_cordic": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cor_mode_i", "type": "t_CORDIC_MODE", "width": "" }, { "direction": "in", "name": "cor_submode_i", "type": "t_CORDIC_SUBMODE", "width": "" }, { "direction": "in", "name": "lim_x_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "lim_y_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "x0_i", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "in", "name": "y0_i", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "in", "name": "z0_i", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "out", "name": "xn_o", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "out", "name": "yn_o", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "out", "name": "zn_o", "type": "std_logic_vector", "width": "g_M-1 downto 0" }, { "direction": "out", "name": "lim_x_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "lim_y_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rst_o", "type": "std_logic", "width": "" } ], "gc_cordic_top": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "mode_i", "type": "t_CORDIC_MODE", "width": "" }, { "direction": "in", "name": "submode_i", "type": "t_CORDIC_SUBMODE", "width": "" }, { "direction": "in", "name": "x_i", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "in", "name": "y_i", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "in", "name": "z_i", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "in", "name": "valid_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "lim_x_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "lim_y_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "x_o", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "out", "name": "y_o", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "out", "name": "z_o", "type": "std_logic_vector", "width": "g_WIDTH-1 downto 0" }, { "direction": "out", "name": "valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "mode_o", "type": "t_CORDIC_MODE", "width": "" }, { "direction": "out", "name": "submode_o", "type": "t_CORDIC_SUBMODE", "width": "" } ], "gc_crc_gen": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "en_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "half_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "data_i", "type": "std_logic_vector", "width": "g_data_width - 1 downto 0" }, { "direction": "in", "name": "restart_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "match_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "crc_o", "type": "std_logic_vector", "width": "g_polynomial'length - 1 downto 0" } ], "gc_dec_8b10b": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_10b_i", "type": "std_logic_vector", "width": "9 downto 0" }, { "direction": "out", "name": "ctrl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "code_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rdisp_err_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_8b_o", "type": "std_logic_vector", "width": "7 downto 0" } ], "gc_delay_gen": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_data_width - 1 downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_data_width - 1 downto 0" } ], "gc_ds182x_interface": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_p_i", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "onewire_b", "type": "std_logic", "width": "" }, { "direction": "out", "name": "id_o", "type": "std_logic_vector", "width": "63 downto 0" }, { "direction": "out", "name": "temper_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "id_read_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "id_ok_o", "type": "std_logic", "width": "" } ], "gc_dual_pi_controller": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_sysclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "phase_err_i", "type": "std_logic_vector", "width": "g_error_bits-1 downto 0" }, { "direction": "in", "name": "phase_err_stb_p_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "freq_err_i", "type": "std_logic_vector", "width": "g_error_bits-1 downto 0" }, { "direction": "in", "name": "freq_err_stb_p_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "mode_sel_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dac_val_o", "type": "std_logic_vector", "width": "g_dacval_bits-1 downto 0" }, { "direction": "out", "name": "dac_val_stb_p_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pll_pcr_enable_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pll_pcr_force_f_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pll_fbgr_f_kp_i", "type": "std_logic_vector", "width": "g_coef_bits-1 downto 0" }, { "direction": "in", "name": "pll_fbgr_f_ki_i", "type": "std_logic_vector", "width": "g_coef_bits-1 downto 0" }, { "direction": "in", "name": "pll_pbgr_p_kp_i", "type": "std_logic_vector", "width": "g_coef_bits-1 downto 0" }, { "direction": "in", "name": "pll_pbgr_p_ki_i", "type": "std_logic_vector", "width": "g_coef_bits-1 downto 0" } ], "gc_dyn_extend_pulse": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pulse_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "len_i", "type": "std_logic_vector", "width": "g_len_width-1 downto 0" }, { "direction": "out", "name": "extended_o", "type": "std_logic", "width": "" } ], "gc_dyn_glitch_filt": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "len_i", "type": "std_logic_vector", "width": "g_len_width-1 downto 0" }, { "direction": "in", "name": "dat_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dat_o", "type": "std_logic", "width": "" } ], "gc_enc_8b10b": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ctrl_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_8b_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "err_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dispar_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dispar_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "out_10b_o", "type": "std_logic_vector", "width": "9 downto 0" } ], "gc_freq_meas": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_freq_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_freq_ena_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "freq_low_thr_sys_i", "type": "std_logic_vector", "width": "g_COUNTER_WIDTH-1 downto 0" }, { "direction": "in", "name": "freq_high_thr_sys_i", "type": "std_logic_vector", "width": "g_COUNTER_WIDTH-1 downto 0" }, { "direction": "out", "name": "freq_value_sys_o", "type": "std_logic_vector", "width": "g_COUNTER_WIDTH-1 downto 0" }, { "direction": "out", "name": "freq_value_freq_o", "type": "std_logic_vector", "width": "g_COUNTER_WIDTH-1 downto 0" }, { "direction": "out", "name": "freq_valid_sys_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_valid_freq_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_ok_sys_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_ok_freq_o", "type": "std_logic", "width": "" } ], "gc_frequency_meter": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_p1_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_o", "type": "std_logic_vector", "width": "g_COUNTER_BITS-1 downto 0" }, { "direction": "out", "name": "freq_valid_o", "type": "std_logic", "width": "" } ], "gc_integer_divide": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "is_rem_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "is_signed_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "a_i", "type": "std_logic_vector", "width": "g_BITS-1 downto 0" }, { "direction": "in", "name": "b_i", "type": "std_logic_vector", "width": "g_BITS-1 downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_BITS-1 downto 0" }, { "direction": "in", "name": "start_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ready_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "done_o", "type": "std_logic", "width": "" } ], "gc_iq_demodulator": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sync_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "adc_data_i", "type": "std_logic_vector", "width": "g_N-1 downto 0" }, { "direction": "out", "name": "i_o", "type": "std_logic_vector", "width": "g_N downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_N downto 0" } ], "gc_iq_demodulator_shifted": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sync_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "adc_data_i", "type": "std_logic_vector", "width": "g_N_data-1 downto 0" }, { "direction": "in", "name": "phaseCos_i", "type": "std_logic_vector", "width": "g_N_coeff -1 downto 0" }, { "direction": "in", "name": "phaseSin_i", "type": "std_logic_vector", "width": "g_N_coeff -1 downto 0" }, { "direction": "out", "name": "i_o", "type": "std_logic_vector", "width": "g_N_data downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_N_data downto 0" } ], "gc_iq_modulator": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "en_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sync_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i_i", "type": "std_logic_vector", "width": "g_N-1 downto 0" }, { "direction": "in", "name": "q_i", "type": "std_logic_vector", "width": "g_N-1 downto 0" }, { "direction": "out", "name": "i_o", "type": "std_logic_vector", "width": "g_N-1 downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_N-1 downto 0" } ], "gc_moving_average": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "din_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "dout_o", "type": "std_logic_vector", "width": "g_data_width+g_avg_log2-1 downto 0" }, { "direction": "out", "name": "dout_stb_o", "type": "std_logic", "width": "" } ], "gc_multichannel_frequency_meter": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic_vector", "width": "g_CHANNELS -1 downto 0" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "channel_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "freq_o", "type": "std_logic_vector", "width": "g_COUNTER_BITS-1 downto 0" }, { "direction": "out", "name": "freq_valid_o", "type": "std_logic", "width": "" } ], "gc_negedge": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "data_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pulse_o", "type": "std_logic", "width": "" } ], "gc_pi_regulator": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "en_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "setpoint_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "in", "name": "x_valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "x_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "out", "name": "y_valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "y_o", "type": "std_logic_vector", "width": "g_OUTPUT_BITS-1 downto 0" }, { "direction": "in", "name": "kp_i", "type": "std_logic_vector", "width": "g_GAIN_BITS-1 downto 0" }, { "direction": "in", "name": "ki_i", "type": "std_logic_vector", "width": "g_GAIN_BITS-1 downto 0" }, { "direction": "out", "name": "lim_o", "type": "std_logic", "width": "" } ], "gc_pipelined_fir_filter": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "coefs_i", "type": "t_FIR_COEF_ARRAY", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "in", "name": "d_valid_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "d_o", "type": "std_logic_vector", "width": "g_OUTPUT_BITS-1 downto 0" }, { "direction": "out", "name": "d_valid_o", "type": "std_logic", "width": "" } ], "gc_posedge": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "data_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pulse_o", "type": "std_logic", "width": "" } ], "gc_reset": [ { "direction": "in", "name": "free_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "locked_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clks_i", "type": "std_logic_vector", "width": "g_clocks-1 downto 0" }, { "direction": "out", "name": "rstn_o", "type": "std_logic_vector", "width": "g_clocks-1 downto 0" } ], "gc_reset_multi_aasd": [ { "direction": "in", "name": "arst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clks_i", "type": "std_logic_vector", "width": "g_CLOCKS-1 downto 0" }, { "direction": "out", "name": "rst_n_o", "type": "std_logic_vector", "width": "g_CLOCKS-1 downto 0" } ], "gc_rr_arbiter": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "req_i", "type": "std_logic_vector", "width": "g_size-1 downto 0" }, { "direction": "out", "name": "grant_o", "type": "std_logic_vector", "width": "g_size-1 downto 0" }, { "direction": "out", "name": "grant_comb_o", "type": "std_logic_vector", "width": "g_size-1 downto 0" } ], "gc_scrambler_descrambler": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "aux_i", "type": "std_logic_vector", "width": "g_AUX_SIZE-1 downto 0" }, { "direction": "in", "name": "data_i", "type": "std_logic_vector", "width": "g_DATA_SIZE-1 downto 0" }, { "direction": "out", "name": "valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "aux_o", "type": "std_logic_vector", "width": "g_AUX_SIZE-1 downto 0" }, { "direction": "out", "name": "data_o", "type": "std_logic_vector", "width": "g_DATA_SIZE-1 downto 0" } ], "gc_serial_dac": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "value_i", "type": "std_logic_vector", "width": "g_num_data_bits-1 downto 0" }, { "direction": "in", "name": "cs_sel_i", "type": "std_logic_vector", "width": "g_num_cs_select-1 downto 0" }, { "direction": "in", "name": "load_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sclk_divsel_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "dac_cs_n_o", "type": "std_logic_vector", "width": "g_num_cs_select-1 downto 0" }, { "direction": "out", "name": "dac_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dac_sdata_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dac_sel_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "busy_o", "type": "std_logic", "width": "" } ], "gc_sfp_i2c_adapter": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sda_en_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sfp_det_valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sfp_data_i", "type": "std_logic_vector", "width": "127 downto 0" } ], "gc_single_reset_gen": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_signals_n_a_i", "type": "std_logic_vector", "width": "g_rst_in_num-1 downto 0" }, { "direction": "out", "name": "rst_n_o", "type": "std_logic", "width": "" } ], "gc_soft_ramp_switch": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rate_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "on_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "kill_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "is_on_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "is_off_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "busy_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "x_valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "x0_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "in", "name": "x1_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "in", "name": "x2_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "in", "name": "x3_i", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "out", "name": "y_valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "y0_o", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "out", "name": "y1_o", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "out", "name": "y2_o", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" }, { "direction": "out", "name": "y3_o", "type": "std_logic_vector", "width": "g_DATA_BITS-1 downto 0" } ], "gc_sync_word_rd": [ { "direction": "in", "name": "clk_out_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_out_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_in_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "data_in_i", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "in", "name": "rd_out_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ack_out_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "data_out_o", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "out", "name": "rd_in_o", "type": "std_logic", "width": "" } ], "gc_word_packer": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_input_width-1 downto 0" }, { "direction": "in", "name": "d_valid_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "d_req_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "flush_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_output_width-1 downto 0" }, { "direction": "out", "name": "q_valid_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "q_req_i", "type": "std_logic", "width": "" } ], "generic_async_fifo_mixedw": [ { "direction": "in", "name": "rst_n_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_wr_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_wr_width-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_count_o", "type": "std_logic_vector", "width": "f_log2_size(g_size * ((g_rd_width + g_wr_width - 1) / g_wr_width)) downto 0" }, { "direction": "in", "name": "clk_rd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_rd_width-1 downto 0" }, { "direction": "in", "name": "rd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_empty_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_count_o", "type": "std_logic_vector", "width": "f_log2_size(g_size * ((g_rd_width + g_wr_width - 1) / g_rd_width)) downto 0" } ], "generic_dpram_dualclock": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clka_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bwea_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "wea_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "aa_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "da_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qa_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "clkb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bweb_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "web_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ab_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "db_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qb_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" } ], "generic_dpram_inst_7series": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clka_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bwea_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "wea_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "aa_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "da_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qa_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "clkb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bweb_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "web_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ab_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "db_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qb_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" } ], "generic_dpram_sameclock": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bwea_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "wea_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "aa_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "da_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qa_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "bweb_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "web_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ab_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "db_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "qb_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" } ], "generic_shiftreg_fifo": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "rd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "almost_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_valid_o", "type": "std_logic", "width": "" } ], "generic_spram": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bwe_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "a_i", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" } ], "lm32_cpu_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_cpu_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_dcache_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_dcache_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_debug_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_debug_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_debug_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_debug_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_decoder_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_icache_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_icache_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_icache_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_icache_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_icache_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": 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}, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_instruction_unit_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_interrupt_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_jtag_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_jtag_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_jtag_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_load_store_unit_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_mc_arithmetic_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[`LM32_INTERRUPT_RNG]" }, { "direction": "in", "name": "user_result", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "in", "name": "user_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "user_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "user_opcode", "type": "wire", "width": "[`LM32_USER_OPCODE_RNG]" }, { "direction": "out", "name": "user_operand_0", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "user_operand_1", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[`LM32_BYTE_SELECT_RNG]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[`LM32_CTYPE_RNG]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[`LM32_BTYPE_RNG]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[`LM32_WORD_RNG]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[`LM32_BYTE_SELECT_RNG]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[`LM32_CTYPE_RNG]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[`LM32_BTYPE_RNG]" } ], "lm32_top_full": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_full_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_medium": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": 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"branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_medium_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", 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"name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_medium_icache": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_medium_icache_debug": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", 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"branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_minimal": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_result_sel_0", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "d_result_sel_1", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "x_result_sel_csr", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_mc_arith", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_sext", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_logic", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_add", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_compare", "type": "wire", "width": "" }, { "direction": "out", "name": "m_result_sel_shift", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_load", "type": "wire", "width": "" }, { "direction": "out", "name": "w_result_sel_mul", "type": "wire", "width": "" }, { "direction": "out", "name": "x_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", 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"name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "lm32_top_wr_node": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "interrupt", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "I_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "I_RTY_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_DAT_I", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "D_ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "D_RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "I_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "I_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "I_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "I_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "I_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "D_DAT_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_ADR_O", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "D_CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_SEL_O", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "D_STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_WE_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_CTI_O", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "D_LOCK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "D_BTE_O", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "stall_d", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_x", "type": "wire", "width": "" }, { "direction": "in", "name": "divide_d", "type": "wire", "width": "" }, { "direction": "in", "name": "modulus_d", "type": "wire", "width": "" }, { "direction": "in", "name": "operand_0_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "operand_1_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "result_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "divide_by_zero_x", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_a", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_x", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_m", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_operand_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "load_store_address_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "load_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "load_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "store_q_m", "type": "wire", "width": "" }, { "direction": "in", "name": "sign_extend_x", "type": "wire", "width": "" }, { "direction": "in", "name": "size_x", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "dflush", "type": "wire", "width": "" }, { "direction": "in", "name": "d_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "d_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "dcache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "load_data_w", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "stall_wb_load", "type": "wire", "width": "" }, { "direction": "out", "name": "d_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "d_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "d_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "d_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "d_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "in", "name": "instruction", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", 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"name": "m_bypass_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "read_enable_0", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_0", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "read_enable_1", "type": "wire", "width": "" }, { "direction": "out", "name": "read_idx_1", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "write_enable", "type": "wire", "width": "" }, { "direction": "out", "name": "write_idx", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "immediate", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "branch_offset", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "load", "type": "wire", "width": "" }, { "direction": "out", "name": "store", "type": "wire", "width": "" }, { "direction": "out", "name": "size", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "sign_extend", "type": "wire", "width": "" }, { "direction": "out", "name": "adder_op", "type": "wire", "width": "" }, { "direction": "out", "name": "logic_op", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "direction", "type": "wire", "width": "" }, { "direction": "out", "name": "divide", "type": "wire", "width": "" }, { "direction": "out", "name": "modulus", "type": "wire", "width": "" }, { "direction": "out", "name": "branch", "type": "wire", "width": "" }, { "direction": "out", "name": "branch_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "condition", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "bi_conditional", "type": "wire", "width": "" }, { "direction": "out", "name": "bi_unconditional", "type": "wire", "width": "" }, { "direction": "out", "name": "scall", "type": "wire", "width": "" }, { "direction": "out", "name": "eret", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "stall_f", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_d", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_taken_d", "type": "wire", "width": "" }, { "direction": "in", "name": "address_a", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "address_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "read_enable_f", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "refill_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "iflush", "type": "wire", "width": "" }, { "direction": "out", "name": "stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "refill_address", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "inst", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_x", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "address_m", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "store_byte_select", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "load_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "valid_f", "type": "wire", "width": "" }, { "direction": "in", "name": "kill_f", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_predict_address_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_x", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "branch_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_mispredict_taken_m", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_target_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "in", "name": "i_dat_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "i_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i_rty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "pc_f", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_d", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_x", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_m", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "pc_w", "type": "wire", "width": "[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2]" }, { "direction": "out", "name": "icache_stall_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_restart_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refill_request", "type": "wire", "width": "" }, { "direction": "out", "name": "icache_refilling", "type": "wire", "width": "" }, { "direction": "out", "name": "i_dat_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_adr_o", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "i_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_sel_o", "type": "wire", "width": "[ (4-1):0]" }, { "direction": "out", "name": "i_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_cti_o", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "i_lock_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i_bte_o", "type": "wire", "width": "[ (2-1):0]" }, { "direction": "out", "name": "bus_error_d", "type": "wire", "width": "" }, { "direction": "out", "name": "instruction_f", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "instruction_d", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "exception", "type": "wire", "width": "" }, { "direction": "in", "name": "eret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr", "type": "wire", "width": "[ (4 -1):0]" }, { "direction": "in", "name": "csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "interrupt_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_update", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_reg_q", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_reg_addr_q", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "jtag_reg_d", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_reg_addr_d", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "break_opcode", "type": "wire", "width": "" }, { "direction": "out", "name": "bret", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_write_enable_x", "type": "wire", "width": "" }, { "direction": "in", "name": "csr_x", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "jtag_csr_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_csr_write_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "jtag_csr", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "in", "name": "bret_q_x", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_x", "type": "wire", "width": "" }, { "direction": "in", "name": "q_x", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_ss", "type": "wire", "width": "" }, { "direction": "out", "name": "dc_re", "type": "wire", "width": "" }, { "direction": "out", "name": "bp_match", "type": "wire", "width": "" }, { "direction": "out", "name": "wp_match", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_read_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "jtag_write_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "jtag_address", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_read_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "jtag_access_complete", "type": "wire", "width": "" }, { "direction": "in", "name": "exception_q_w", "type": "wire", "width": "" }, { "direction": "out", "name": "jtx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jrx_csr_read_data", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "out", "name": "jtag_break", "type": "wire", "width": "" }, { "direction": "out", "name": "jtag_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "non_debug_exception", "type": "wire", "width": "" }, { "direction": "in", "name": "debug_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "x_result_sel_shift", "type": "wire", "width": "" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_pc", "type": "wire", "width": "[ ((32-2)+2-1):2]" }, { "direction": "out", "name": "trace_pc_valid", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_exception", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_eid", "type": "wire", "width": "[ (3-1):0]" }, { "direction": "out", "name": "trace_eret", "type": "wire", "width": "" }, { "direction": "out", "name": "trace_bret", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_i_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_d_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "iram_d_en_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_csr_write_data_i", "type": "wire", "width": "[ (32-1):0]" }, { "direction": "in", "name": "dbg_csr_addr_i", "type": "wire", "width": "[ (5-1):0]" }, { "direction": "out", "name": "dbg_exception_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dbg_break_i", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_d_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "iram_d_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "iram_stall_request_x", "type": "wire", "width": "" }, { "direction": "out", "name": "iram_i_en_o", "type": "wire", "width": "" } ], "mpsoc_int_gen": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "irq_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_awaddr", "type": "std_logic_vector", "width": "48 downto 0" }, { "direction": "out", "name": "S_AXI_awburst", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "S_AXI_awcache", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "S_AXI_awid", "type": "std_logic_vector", "width": "5 downto 0" }, { "direction": "out", "name": "S_AXI_awlen", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "S_AXI_awlock", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_awprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "S_AXI_awready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_awsize", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "S_AXI_awuser", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_awvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_wdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "S_AXI_wlast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AXI_wready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AXI_wstrb", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "S_AXI_wvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AXI_bid", "type": "std_logic_vector", "width": "5 downto 0" }, { "direction": "out", "name": "S_AXI_bready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AXI_bresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "S_AXI_bvalid", "type": "std_logic", "width": "" } ], "pcie_wb": [ { "direction": "in", "name": "clk125_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cal_clk50_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pcie_refclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pcie_rstn_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pcie_rx_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "pcie_tx_o", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "master_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "master_rstn_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "in", "name": "slave_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_rstn_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" } ], "secded_ecc": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "a_i", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bwe_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "re_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "done_r_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "done_w_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "a_ram_o", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "d_ram_i", "type": "std_logic_vector", "width": "38 downto 0" }, { "direction": "out", "name": "q_ram_o", "type": "std_logic_vector", "width": "38 downto 0" }, { "direction": "out", "name": "we_ram_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "re_ram_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "valid_ram_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "lock_req_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "lock_grant_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "single_error_p_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "double_error_p_o", "type": "std_logic", "width": "" } ], "spi_top": [ { "direction": "out", "name": "int_o", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[32-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ss_pad_o", "type": "wire", "width": "[SPI_SS_NB-1:0]" }, { "direction": "out", "name": "sclk_pad_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mosi_pad_o", "type": "wire", "width": "" }, { "direction": "in", "name": "miso_pad_i", "type": "wire", "width": "" } ], "uart_wb_slave": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_addr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "wb_data_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_data_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_sr_tx_busy_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_sr_rx_rdy_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "uart_bcr_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "uart_tdr_tx_data_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "uart_tdr_tx_data_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "uart_tdr_tx_data_load_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_rdr_rx_data_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "rdr_rack_o", "type": "std_logic", "width": "" } ], "v6_hwfifo_wraper": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_wr_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_rd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "d_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "q_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "rd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_empty_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_almost_empty_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_almost_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_count_o", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" }, { "direction": "out", "name": "wr_count_o", "type": "std_logic_vector", "width": "f_log2_size(g_size)-1 downto 0" } ], "voter_vec_status": [ { "direction": "in", "name": "a", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "in", "name": "b", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "in", "name": "c", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "out", "name": "res", "type": "std_logic_vector", "width": "g_WIDTH - 1 downto 0" }, { "direction": "out", "name": "err", "type": "std_logic", "width": "" } ], "wb16_to_wb32": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb16_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb16_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "wb32_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "wb32_o", "type": "t_wishbone_master_out", "width": "" } ], "wb_axi4lite_bridge": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ARVALID", "type": "std_logic", "width": "" }, { "direction": "in", "name": "AWVALID", "type": "std_logic", "width": "" }, { "direction": "in", "name": "BREADY", "type": "std_logic", "width": "" }, { "direction": "in", "name": "RREADY", "type": "std_logic", "width": "" }, { "direction": "in", "name": "WLAST", "type": "std_logic", "width": "" }, { "direction": "in", "name": "WVALID", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ARADDR", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "AWADDR", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "WDATA", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "WSTRB", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "ARREADY", "type": "std_logic", "width": "" }, { "direction": "out", "name": "AWREADY", "type": "std_logic", "width": "" }, { "direction": "out", "name": "BVALID", "type": "std_logic", "width": "" }, { "direction": "out", "name": "RLAST", "type": "std_logic", "width": "" }, { "direction": "out", "name": "RVALID", "type": "std_logic", "width": "" }, { "direction": "out", "name": "WREADY", "type": "std_logic", "width": "" }, { "direction": "out", "name": "BRESP", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "RRESP", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "RDATA", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_adr", "type": "std_logic_vector", "width": "c_wishbone_address_width-1 downto 0" }, { "direction": "out", "name": "wb_dat_m2s", "type": "std_logic_vector", "width": "c_wishbone_data_width-1 downto 0" }, { "direction": "out", "name": "wb_sel", "type": "std_logic_vector", "width": "c_wishbone_data_width/8-1 downto 0" }, { "direction": "out", "name": "wb_cyc", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_stb", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_we", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_dat_s2m", "type": "std_logic_vector", "width": "c_wishbone_data_width-1 downto 0" }, { "direction": "in", "name": "wb_err", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_rty", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_ack", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stall", "type": "std_logic", "width": "" } ], "wb_conmax_top": [ { "direction": "in", "name": "wb_masters_i", "type": "t_conmax_masters_i", "width": "" }, { "direction": "out", "name": "wb_masters_o", "type": "t_conmax_masters_o", "width": "" }, { "direction": "in", "name": "wb_slaves_i", "type": "t_conmax_slaves_i", "width": "" }, { "direction": "out", "name": "wb_slaves_o", "type": "t_conmax_slaves_o", "width": "" } ], "wb_i2c_bridge": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "scl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "scl_en_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sda_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sda_en_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2c_addr_i", "type": "std_logic_vector", "width": "6 downto 0" }, { "direction": "out", "name": "tip_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "err_p_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wdto_p_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wbm_stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wbm_cyc_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wbm_sel_o", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "wbm_we_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wbm_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wbm_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wbm_adr_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wbm_ack_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wbm_rty_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wbm_err_i", "type": "std_logic", "width": "" } ], "wb_irq_lm32": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dwb_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "dwb_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "iwb_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "iwb_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "irq_slave_o", "type": "t_wishbone_slave_out_array", "width": "g_msi_queues-1 downto 0" }, { "direction": "in", "name": "irq_slave_i", "type": "t_wishbone_slave_in_array", "width": "g_msi_queues-1 downto 0" }, { "direction": "out", "name": "ctrl_slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "ctrl_slave_i", "type": "t_wishbone_slave_in", "width": "" } ], "wb_irq_master": [ { "direction": "out", "name": "irq_master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "irq_master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "ctrl_slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "ctrl_slave_i", "type": "t_wishbone_slave_in", "width": "" } ], "wb_irq_timer": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_sys_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "tm_tai8ns_i", "type": "std_logic_vector", "width": "63 downto 0" }, { "direction": "out", "name": "ctrl_slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "ctrl_slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "irq_master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "irq_master_i", "type": "t_wishbone_master_in", "width": "" } ], "wb_serial_lcd": [ { "direction": "in", "name": "slave_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_rstn_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "di_clk_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "di_scp_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "di_lp_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "di_flm_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "di_dat_o", "type": "std_logic", "width": "" } ], "wb_skidpad2": [ { "direction": "in", "name": "stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "adr_i", "type": "std_logic_vector", "width": "g_adrbits-1 downto 0" }, { "direction": "in", "name": "dat_i", "type": "std_logic_vector", "width": "g_datbits-1 downto 0" }, { "direction": "in", "name": "sel_i", "type": "std_logic_vector", "width": "(g_datbits/8)-1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "stall_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "adr_o", "type": "std_logic_vector", "width": "g_adrbits-1 downto 0" }, { "direction": "out", "name": "dat_o", "type": "std_logic_vector", "width": "g_datbits-1 downto 0" }, { "direction": "out", "name": "sel_o", "type": "std_logic_vector", "width": "(g_datbits/8)-1 downto 0" }, { "direction": "out", "name": "we_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "stall_i", "type": "std_logic", "width": "" } ], "wbgen2_dpssram": [ { "direction": "in", "name": "clk_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "addr_a_i", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "addr_b_i", "type": "std_logic_vector", "width": "g_addr_width-1 downto 0" }, { "direction": "in", "name": "data_a_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "data_b_i", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "data_a_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "out", "name": "data_b_o", "type": "std_logic_vector", "width": "g_data_width-1 downto 0" }, { "direction": "in", "name": "bwsel_a_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "bwsel_b_i", "type": "std_logic_vector", "width": "(g_data_width+7)/8-1 downto 0" }, { "direction": "in", "name": "rd_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rd_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_b_i", "type": "std_logic", "width": "" } ], "wbgen2_eic": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" } ], "wbgen2_fifo_async": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rd_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rd_req_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_data_o", "type": "std_logic_vector", "width": "g_width-1 downto 0" }, { "direction": "out", "name": "rd_empty_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rd_usedw_o", "type": "std_logic_vector", "width": "g_usedw_size -1 downto 0" }, { "direction": "in", "name": "wr_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_req_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wr_data_i", "type": "std_logic_vector", "width": "g_width-1 downto 0" }, { "direction": "out", "name": "wr_empty_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_full_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wr_usedw_o", "type": "std_logic_vector", "width": "g_usedw_size -1 downto 0" } ], "xaxi4lite_wb_bridge": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "axi4_master_o", "type": "t_axi4_lite_master_out_32", "width": "" }, { "direction": "in", "name": "axi4_master_i", "type": "t_axi4_lite_master_in_32", "width": "" } ], "xwb_async_bridge": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cpu_cs_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cpu_wr_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cpu_rd_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cpu_bs_n_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "cpu_addr_i", "type": "std_logic_vector", "width": "g_cpu_address_width-1 downto 0" }, { "direction": "inout", "name": "cpu_data_b", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "cpu_nwait_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" } ], "xwb_bus_fanout": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in_array", "width": "0 to g_num_outputs-1" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out_array", "width": "0 to g_num_outputs-1" } ], "xwb_clock_monitor": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic_vector", "width": "g_num_clocks-1 downto 0" }, { "direction": "in", "name": "pps_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_conmax": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in_array", "width": "0 to g_num_slaves-1" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out_array", "width": "0 to g_num_slaves-1" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in_array", "width": "0 to g_num_masters-1" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out_array", "width": "0 to g_num_masters-1" } ], "xwb_dpram": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave1_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave1_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "slave2_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave2_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_dpram_mixed": [ { "direction": "in", "name": "clk_slave1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_slave2_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave1_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave1_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "slave2_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave2_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_ds182x_readout": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "pps_p_i", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "onewire_b", "type": "std_logic", "width": "" } ], "xwb_fine_pulse_gen": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_sys_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ser_ext_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ext_trigger_p_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_p_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pulse_o", "type": "std_logic_vector", "width": "g_num_channels-1 downto 0" }, { "direction": "out", "name": "clk_par_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_gpio_port": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" }, { "direction": "inout", "name": "gpio_b", "type": "std_logic_vector", "width": "g_num_pins-1 downto 0" }, { "direction": "out", "name": "gpio_out_o", "type": "std_logic_vector", "width": "g_num_pins-1 downto 0" }, { "direction": "in", "name": "gpio_in_i", "type": "std_logic_vector", "width": "g_num_pins-1 downto 0" }, { "direction": "out", "name": "gpio_oen_o", "type": "std_logic_vector", "width": "g_num_pins-1 downto 0" } ], "xwb_i2c_master": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" }, { "direction": "out", "name": "int_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_pad_i", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" }, { "direction": "out", "name": "scl_pad_o", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" }, { "direction": "out", "name": "scl_padoen_o", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" }, { "direction": "in", "name": "sda_pad_i", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" }, { "direction": "out", "name": "sda_pad_o", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" }, { "direction": "out", "name": "sda_padoen_o", "type": "std_logic_vector", "width": "g_num_interfaces-1 downto 0" } ], "xwb_indirect": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_wb_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "master_wb_o", "type": "t_wishbone_master_out", "width": "" } ], "xwb_lm32_mcs": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "irq_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "host_wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "host_wb_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "dbg_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dbg_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dwb_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "dwb_i", "type": "t_wishbone_master_in", "width": "" } ], "xwb_metadata": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_onewire_master": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" }, { "direction": "out", "name": "int_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "owr_pwren_o", "type": "std_logic_vector", "width": "g_num_ports -1 downto 0" }, { "direction": "out", "name": "owr_en_o", "type": "std_logic_vector", "width": "g_num_ports -1 downto 0" }, { "direction": "in", "name": "owr_i", "type": "std_logic_vector", "width": "g_num_ports -1 downto 0" } ], "xwb_register": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" } ], "xwb_register_link": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" } ], "xwb_remapper": [ { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" } ], "xwb_sdb_crossbar": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in_array", "width": "g_num_masters-1 downto 0" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out_array", "width": "g_num_masters-1 downto 0" }, { "direction": "in", "name": "msi_master_i", "type": "t_wishbone_master_in_array", "width": "g_num_masters-1 downto 0" }, { "direction": "out", "name": "msi_master_o", "type": "t_wishbone_master_out_array", "width": "g_num_masters-1 downto 0" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in_array", "width": "g_num_slaves -1 downto 0" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out_array", "width": "g_num_slaves -1 downto 0" }, { "direction": "in", "name": "msi_slave_i", "type": "t_wishbone_slave_in_array", "width": "g_num_slaves -1 downto 0" }, { "direction": "out", "name": "msi_slave_o", "type": "t_wishbone_slave_out_array", "width": "g_num_slaves -1 downto 0" } ], "xwb_simple_pwm": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "pwm_o", "type": "std_logic_vector", "width": "g_num_channels-1 downto 0" } ], "xwb_spi": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" }, { "direction": "out", "name": "int_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pad_cs_o", "type": "std_logic_vector", "width": "g_num_slaves-1 downto 0" }, { "direction": "out", "name": "pad_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pad_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pad_miso_i", "type": "std_logic", "width": "" } ], "xwb_split": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in_array", "width": "1 downto 0" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out_array", "width": "1 downto 0" } ], "xwb_streamer": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "r_master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "r_master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "w_master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "w_master_o", "type": "t_wishbone_master_out", "width": "" } ], "xwb_tics": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" } ], "xwb_vic": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "irqs_i", "type": "std_logic_vector", "width": "g_num_interrupts-1 downto 0" }, { "direction": "out", "name": "irq_master_o", "type": "std_logic", "width": "" } ], "xwb_vuart": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "host_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "host_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "in", "name": "board_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "board_o", "type": "t_wishbone_slave_out", "width": "" } ], "xwb_xc7_fw_update": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "flash_cs_n_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "flash_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "flash_miso_i", "type": "std_logic", "width": "" } ], "xwb_xil_multiboot": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wbs_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wbs_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "spi_cs_n_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_miso_i", "type": "std_logic", "width": "" } ], "xwb_xilinx_fpga_loader": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "desc_o", "type": "t_wishbone_device_descriptor", "width": "" }, { "direction": "out", "name": "xlx_cclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "xlx_din_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "xlx_program_b_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "xlx_init_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "xlx_done_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "xlx_suspend_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "xlx_m_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "boot_trig_p1_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "boot_exit_p1_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "boot_en_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_logic_vector", "width": "7 downto 0" } ] }, "top_modules": [ "altera_async_fifo", "altera_sync_fifo", "axi4lite32_axi4full64_bridge", "axi4lite_axi4full_bridge", "axi4lite_i2c_master", "axi_gpio_expander", "cheby_dpssram", "dec_8b10b_ctrl", "dec_8b10b_disp", "dec_8b10b_lut", "flash_top", "gc_arbitrated_mux", "gc_argb_led_drv", "gc_async_counter_diff", "gc_async_signals_input_stage", "gc_bicolor_led_ctrl", "gc_cic", "gc_cic_combs", "gc_cic_decimator", "gc_cic_integrators", "gc_cic_ratio_change_detect", "gc_comparator", "gc_cordic", "gc_cordic_top", "gc_crc_gen", "gc_dec_8b10b", "gc_delay_gen", "gc_ds182x_interface", "gc_dual_pi_controller", "gc_dyn_extend_pulse", "gc_dyn_glitch_filt", "gc_enc_8b10b", "gc_freq_meas", "gc_frequency_meter", "gc_integer_divide", "gc_iq_demodulator", "gc_iq_demodulator_shifted", "gc_iq_modulator", "gc_moving_average", "gc_multichannel_frequency_meter", "gc_negedge", "gc_pi_regulator", "gc_pipelined_fir_filter", "gc_posedge", "gc_reset", "gc_reset_multi_aasd", "gc_rr_arbiter", "gc_scrambler_descrambler", "gc_serial_dac", "gc_sfp_i2c_adapter", "gc_single_reset_gen", "gc_soft_ramp_switch", "gc_sync_word_rd", "gc_word_packer", "generic_async_fifo_mixedw", "generic_dpram_dualclock", "generic_dpram_inst_7series", "generic_dpram_sameclock", "generic_shiftreg_fifo", "generic_spram", "lm32_cpu_full_debug", "lm32_cpu_medium", "lm32_cpu_medium_debug", "lm32_cpu_medium_icache", "lm32_cpu_medium_icache_debug", "lm32_cpu_minimal", "lm32_cpu_wr_node", "lm32_dcache_full", "lm32_dcache_full_debug", "lm32_debug_full_debug", "lm32_debug_medium_debug", "lm32_debug_medium_icache_debug", "lm32_debug_wr_node", "lm32_decoder_full", "lm32_decoder_full_debug", "lm32_decoder_medium", "lm32_decoder_medium_debug", "lm32_decoder_medium_icache", "lm32_decoder_medium_icache_debug", "lm32_decoder_minimal", "lm32_decoder_wr_node", "lm32_icache_full", "lm32_icache_full_debug", "lm32_icache_medium_debug", "lm32_icache_medium_icache", "lm32_icache_medium_icache_debug", "lm32_instruction_unit_full", "lm32_instruction_unit_full_debug", "lm32_instruction_unit_medium", "lm32_instruction_unit_medium_debug", "lm32_instruction_unit_medium_icache", "lm32_instruction_unit_medium_icache_debug", "lm32_instruction_unit_minimal", "lm32_instruction_unit_wr_node", "lm32_interrupt_full", "lm32_interrupt_full_debug", "lm32_interrupt_medium", "lm32_interrupt_medium_debug", "lm32_interrupt_medium_icache", "lm32_interrupt_medium_icache_debug", "lm32_interrupt_minimal", "lm32_interrupt_wr_node", "lm32_jtag_full_debug", "lm32_jtag_medium_debug", "lm32_jtag_medium_icache_debug", "lm32_load_store_unit_full", "lm32_load_store_unit_full_debug", "lm32_load_store_unit_medium", "lm32_load_store_unit_medium_debug", "lm32_load_store_unit_medium_icache", "lm32_load_store_unit_medium_icache_debug", "lm32_load_store_unit_minimal", "lm32_load_store_unit_wr_node", "lm32_mc_arithmetic_full", "lm32_mc_arithmetic_full_debug", "lm32_mc_arithmetic_medium", "lm32_mc_arithmetic_medium_debug", "lm32_mc_arithmetic_medium_icache", "lm32_mc_arithmetic_medium_icache_debug", "lm32_mc_arithmetic_minimal", "lm32_mc_arithmetic_wr_node", "lm32_top", "lm32_top_full", "lm32_top_full_debug", "lm32_top_medium", "lm32_top_medium_debug", "lm32_top_medium_icache", "lm32_top_medium_icache_debug", "lm32_top_minimal", "lm32_top_wr_node", "mpsoc_int_gen", "pcie_wb", "secded_ecc", "spi_top", "uart_wb_slave", "v6_hwfifo_wraper", "voter_vec_status", "wb16_to_wb32", "wb_axi4lite_bridge", "wb_conmax_top", "wb_i2c_bridge", "wb_irq_lm32", "wb_irq_master", "wb_irq_timer", "wb_serial_lcd", "wb_skidpad2", "wbgen2_dpssram", "wbgen2_eic", "wbgen2_fifo_async", "xaxi4lite_wb_bridge", "xwb_async_bridge", "xwb_bus_fanout", "xwb_clock_bridge", "xwb_clock_monitor", "xwb_conmax", "xwb_dpram", "xwb_dpram_mixed", "xwb_ds182x_readout", "xwb_fine_pulse_gen", "xwb_gpio_port", "xwb_i2c_master", "xwb_indirect", "xwb_lm32_mcs", "xwb_metadata", "xwb_onewire_master", "xwb_register", "xwb_register_link", "xwb_remapper", "xwb_sdb_crossbar", "xwb_simple_pwm", "xwb_spi", "xwb_split", "xwb_streamer", "xwb_tics", "xwb_vic", "xwb_vuart", "xwb_xc7_fw_update", "xwb_xil_multiboot", "xwb_xilinx_fpga_loader" ] }, { "namespace": "open-logic", "name": "olo_axi_lite_slave", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements an AXI-Lite Slave Interface, which can be used to access registers and memory. On the user-side it provides a simple read/write/address/data interface.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite", "olo", "open", "slave" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_axi_pkg_protocol", "olo_base_pkg_array", "olo_base_pkg_logic", "olo_base_pkg_math" ], "top_ports": { "olo_axi_lite_slave": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AxiLite_ArAddr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AxiLite_ArValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AxiLite_ArReady", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AxiLite_AwAddr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AxiLite_AwValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AxiLite_AwReady", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AxiLite_WData", "type": "std_logic_vector", "width": "AxiDataWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AxiLite_WStrb", "type": "std_logic_vector", "width": "(AxiDataWidth_g/8) - 1 downto 0" }, { "direction": "in", "name": "S_AxiLite_WValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AxiLite_WReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AxiLite_BResp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "S_AxiLite_BValid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AxiLite_BReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AxiLite_RData", "type": "std_logic_vector", "width": "AxiDataWidth_g - 1 downto 0" }, { "direction": "out", "name": "S_AxiLite_RResp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "S_AxiLite_RValid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AxiLite_RReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rb_Addr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "out", "name": "Rb_Wr", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rb_ByteEna", "type": "std_logic_vector", "width": "(AxiDataWidth_g/8) - 1 downto 0" }, { "direction": "out", "name": "Rb_WrData", "type": "std_logic_vector", "width": "AxiDataWidth_g - 1 downto 0" }, { "direction": "out", "name": "Rb_Rd", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rb_RdData", "type": "std_logic_vector", "width": "AxiDataWidth_g - 1 downto 0" }, { "direction": "in", "name": "Rb_RdValid", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_axi_master_full", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a full AXI master. In contrast to olo_axi_master_simple, this entity can do unaligned transfers and it supports different width for the AXI interface than for the data interface.", "license": "", "language": "vhdl-2008-relaxed", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "amba", "axi", "bus", "full", "master", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_axi_pkg_protocol", "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_base_pkg_string" ], "top_ports": { "olo_axi_master_full": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CmdWr_Addr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "in", "name": "CmdWr_Size", "type": "std_logic_vector", "width": "UserTransactionSizeBits_g - 1 downto 0" }, { "direction": "in", "name": "CmdWr_LowLat", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CmdWr_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CmdWr_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CmdRd_Addr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "in", "name": "CmdRd_Size", "type": "std_logic_vector", "width": "UserTransactionSizeBits_g - 1 downto 0" }, { "direction": "in", "name": "CmdRd_LowLat", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CmdRd_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CmdRd_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Wr_Data", "type": "std_logic_vector", "width": "UserDataWidth_g - 1 downto 0" }, { "direction": "in", "name": "Wr_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Wr_Ready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rd_Data", "type": "std_logic_vector", "width": "UserDataWidth_g - 1 downto 0" }, { "direction": "out", "name": "Rd_Last", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rd_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rd_Ready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Wr_Done", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Wr_Error", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rd_Done", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rd_Error", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_Axi_AwAddr", "type": "std_logic_vector", "width": "AxiAddrWidth_g - 1 downto 0" }, { "direction": "out", "name": "M_Axi_AwLen", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "M_Axi_AwSize", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "M_Axi_AwBurst", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "M_Axi_AwLock", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_Axi_AwCache", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "M_Axi_AwProt", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "M_Axi_AwValid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "M_Axi_AwReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_Axi_WData", "type": "std_logic_vector", "width": "AxiDataWidth_g - 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1 downto 0" }, { "direction": "in", "name": "M_Axi_RResp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "M_Axi_RLast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "M_Axi_RValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_Axi_RReady", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_axi_master_simple", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple AXI master. Simple means: It does not support any unaligned reads/writes and it does not do any width conversions.", "license": "", "language": "vhdl-2008-relaxed", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "amba", "axi", "bus", "master", "olo", "open", "simple" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_axi_pkg_protocol", "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_base_pkg_string" ] }, { "namespace": "open-logic", "name": "olo_axi_pl_stage", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements multiple pipeline stages for an axi4 interface.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "amba", "axi", "bus", "olo", "open", "pl" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_attribute" ], "top_ports": { "olo_axi_pl_stage": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AwId", "type": "std_logic_vector", "width": "IdWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AwAddr", "type": "std_logic_vector", "width": "AddrWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AwValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_AwReady", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AwLen", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "S_AwSize", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "S_AwBurst", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "S_AwLock", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_AwCache", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "S_AwProt", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "S_AwQos", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "S_AwUser", "type": "std_logic_vector", "width": "UserWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_AwRegion", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "S_WData", "type": "std_logic_vector", "width": "DataWidth_g - 1 downto 0" }, { "direction": "in", "name": "S_WStrb", "type": "std_logic_vector", "width": "DataWidth_g / 8 - 1 downto 0" }, { "direction": "in", "name": "S_WValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_WReady", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_WLast", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_WUser", "type": "std_logic_vector", "width": "UserWidth_g - 1 downto 0" }, { "direction": "out", "name": "S_BId", "type": "std_logic_vector", "width": "IdWidth_g - 1 downto 0" }, { "direction": "out", "name": "S_BResp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "S_BValid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "S_BReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "S_BUser", "type": "std_logic_vector", "width": "UserWidth_g - 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1 downto 0" }, { "direction": "out", "name": "M_AwRegion", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "M_WData", "type": "std_logic_vector", "width": "DataWidth_g - 1 downto 0" }, { "direction": "out", "name": "M_WStrb", "type": "std_logic_vector", "width": "DataWidth_g / 8 - 1 downto 0" }, { "direction": "out", "name": "M_WValid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "M_WReady", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_WLast", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_WUser", "type": "std_logic_vector", "width": "UserWidth_g - 1 downto 0" }, { "direction": "in", "name": "M_BId", "type": "std_logic_vector", "width": "IdWidth_g - 1 downto 0" }, { "direction": "in", "name": "M_BResp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "M_BValid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "M_BReady", "type": "std_logic", "width": "" }, { "direction": "in", "name": "M_BUser", "type": "std_logic_vector", "width": "UserWidth_g - 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It finds out which is the lowest index of a bit set in the input vecotr.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "decode", "firstbit", "olo", "open" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_logic", "olo_base_pkg_math" ] }, { "namespace": "open-logic", "name": "olo_base_delay", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This is a delay element. It is either emplemented in BRAM or SRL. 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The output width must be an integer multiple of the input width (Wo = n*Wi).", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "converter", "n2xn", "olo", "open", "wconv", "width" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_logic", "olo_base_pkg_math" ] }, { "namespace": "open-logic", "name": "olo_base_wconv_xn2n", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple data-width conversion. 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Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "abs", "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_abs": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_add", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_add function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "add", "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_add": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_B", "type": "std_logic_vector", "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_addsub", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_addsub function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "addsub", "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_addsub": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_B", "type": "std_logic_vector", "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_Add", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_bin_div", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a binary division of two fixed-point numbers using a non-restoring division algorithm.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "bin", "div", "divider", "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_bin_div": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "In_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Num", "type": "std_logic_vector", "width": "fixFmtWidthFromString(NumFmt_g)-1 downto 0" }, { "direction": "in", "name": "In_Denom", "type": "std_logic_vector", "width": "fixFmtWidthFromString(DenomFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Quot", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_cic_dec_par_tdm", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a CIC decimator. It supports one or multiple channels. On the input side the channels are received in parallel (allowing one sample per cycle for every channel).", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "cic", "dec", "decoder", "fix", "olo", "open", "par", "tdm" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_cic_dec_par_tdm": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cfg_Ratio", "type": "std_logic_vector", "width": "log2ceil(Ratio_g)-1 downto 0" }, { "direction": "in", "name": "Cfg_Shift", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "Cfg_GainCorr", "type": "std_logic_vector", "width": "fixFmtWidthFromStringTolerant(GainCorrCoefFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Data", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InFmt_g)*Channels_g-1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Data", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Last", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_fix_cic_dec_tdm", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a CIC decimator. It supports one or multiple channels (time-division-multiplexed). The decimation ratio can either be configurable or fixed.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "cic", "dec", "decoder", "fix", "olo", "open", "tdm" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_cic_dec_tdm": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cfg_Ratio", "type": "std_logic_vector", "width": "log2ceil(Ratio_g) - 1 downto 0" }, { "direction": "in", "name": "Cfg_Shift", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "Cfg_GainCorr", "type": "std_logic_vector", "width": "fixFmtWidthFromStringTolerant(GainCorrCoefFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Data", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_Last", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Data", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Last", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_fix_compare", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_compare function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "compare", "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_compare": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_B", "type": "std_logic_vector", "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_fix_cordic_rot", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a rotating CORDIC algorithm in either pipelined or serial mode.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "cordic", "fix", "olo", "open", "rot" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_cordic_rot": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "In_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Mag", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InMagFmt_g)-1 downto 0" }, { "direction": "in", "name": "In_Ang", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InAngFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_I", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Q", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutFmt_g)-1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_cordic_vect", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a vectoring CORDIC algorithm in either pipelined or serial mode.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "cordic", "fix", "olo", "open", "vect" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_cordic_vect": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "In_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_I", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InFmt_g)-1 downto 0" }, { "direction": "in", "name": "In_Q", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Mag", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutMagFmt_g)-1 downto 0" }, { "direction": "out", "name": "Out_Ang", "type": "std_logic_vector", "width": "fixFmtWidthFromString(OutAngFmt_g)-1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_from_real", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_from_real function as entity. it does NOT include pipeline stages because real numbers are only used for synthesis/simuation. They do not exist in the hardware.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open", "real" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_from_real": [ { "direction": "out", "name": "Out_Value", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_limit", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_limit function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "limit", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_limit": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Data", "type": "std_logic_vector", "width": "fixFmtWidthFromString(InFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_LimLo", "type": "std_logic_vector", "width": "fixFmtWidthFromString(LimLoFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_LimHi", "type": "std_logic_vector", "width": "fixFmtWidthFromString(LimHiFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_mult", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_mult function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "mult", "olo", "open" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ] }, { "namespace": "open-logic", "name": "olo_fix_neg", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_neg function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "neg", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_neg": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_resize", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_resize function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open", "resize" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ] }, { "namespace": "open-logic", "name": "olo_fix_round", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_round function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open", "round" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ] }, { "namespace": "open-logic", "name": "olo_fix_saturate", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_saturate function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open", "saturate" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ] }, { "namespace": "open-logic", "name": "olo_fix_sub", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_sub function as entity. Includes pipeline stages and allows usage from Verilog.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_sub": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "in", "name": "In_B", "type": "std_logic_vector", "width": "fixFmtWidthFromString(BFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Out_Result", "type": "std_logic_vector", "width": "fixFmtWidthFromString(ResultFmt_g) - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_fix_to_real", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements the cl_fix_to_real function as entity. it does NOT include pipeline stages because real numbers are only used for synthesis/simuation. They do not exist in the hardware.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "fix", "olo", "open", "real" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_math", "olo_base_pkg_string", "olo_fix_pkg" ], "top_ports": { "olo_fix_to_real": [ { "direction": "in", "name": "In_A", "type": "std_logic_vector", "width": "fixFmtWidthFromString(AFmt_g) - 1 downto 0" }, { "direction": "out", "name": "Out_Value", "type": "real", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_intf_clk_meas", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity measures the frequency of a clock under the assumption that the frequency of the main-clock (Clk) is exactly correct.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "clk", "clock", "interface", "intf", "meas", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_math" ], "top_ports": { "olo_intf_clk_meas": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ClkTest", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Freq_Hz", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "Freq_Valid", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_intf_debounce", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This is a debouncer for button and switch inputs. It contains a double stage synchronizer to synchronize those inputs to the clock.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "debounce", "interface", "intf", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_math", "olo_base_pkg_string" ], "top_ports": { "olo_intf_debounce": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "DataAsync", "type": "std_logic_vector", "width": "Width_g - 1 downto 0" }, { "direction": "out", "name": "DataOut", "type": "std_logic_vector", "width": "Width_g - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_intf_i2c_master", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple I2C-master (multi master capable)", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "circuit", "i2c", "inter-integrated", "interface", "intf", "master", "olo", "open" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_intf_i2c_master_pkg" ], "top_ports": { "olo_intf_i2c_master": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Cmd_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cmd_Valid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cmd_Command", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "Cmd_Data", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "Cmd_Ack", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cmd_ClkDiv", "type": "std_logic_vector", "width": "ClkDivBits_g - 1 downto 0" }, { "direction": "out", "name": "Resp_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_Command", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "Resp_Data", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "Resp_Ack", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_ArbLost", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_SeqErr", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Status_BusBusy", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Status_CmdTo", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "I2c_Scl", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "I2c_Sda", "type": "std_logic", "width": "" }, { "direction": "in", "name": "I2c_Scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "I2c_Scl_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "I2c_Scl_t", "type": "std_logic", "width": "" }, { "direction": "in", "name": "I2c_Sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "I2c_Sda_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "I2c_Sda_t", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_intf_spi_master", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple SPI-master", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "interface", "intf", "master", "olo", "open", "peripheral", "serial", "spi" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math" ], "top_ports": { "olo_intf_spi_master": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cmd_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Cmd_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Cmd_Slave", "type": "std_logic_vector", "width": "log2ceil(SlaveCnt_g) - 1 downto 0" }, { "direction": "in", "name": "Cmd_Data", "type": "std_logic_vector", "width": "MaxTransWidth_g - 1 downto 0" }, { "direction": "in", "name": "Cmd_TransWidth", "type": "std_logic_vector", "width": "log2ceil(MaxTransWidth_g+1)-1 downto 0" }, { "direction": "out", "name": "Resp_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_Data", "type": "std_logic_vector", "width": "MaxTransWidth_g - 1 downto 0" }, { "direction": "out", "name": "Spi_Sclk", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Spi_Mosi", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Spi_Miso", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Spi_Cs_n", "type": "std_logic_vector", "width": "SlaveCnt_g - 1 downto 0" } ] } }, { "namespace": "open-logic", "name": "olo_intf_spi_slave", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple SPI-slave", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "interface", "intf", "olo", "open", "peripheral", "serial", "slave", "spi" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math" ], "top_ports": { "olo_intf_spi_slave": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rx_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rx_Data", "type": "std_logic_vector", "width": "TransWidth_g - 1 downto 0" }, { "direction": "in", "name": "Tx_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Tx_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Tx_Data", "type": "std_logic_vector", "width": "TransWidth_g - 1 downto 0" }, { "direction": "out", "name": "Resp_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_Sent", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_Aborted", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Resp_CleanEnd", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Spi_Sclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Spi_Mosi", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Spi_Cs_n", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Spi_Miso", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Spi_Miso_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Spi_Miso_t", "type": "std_logic", "width": "" } ] } }, { "namespace": "open-logic", "name": "olo_intf_sync", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This is a simple double-stage synchronizer for synchronizing external signals to the internal system clock.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "interface", "intf", "olo", "open", "sync", "synchronizer", "synchronous" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_attribute" ] }, { "namespace": "open-logic", "name": "olo_intf_uart", "latest": "4.4.1", "versions": [ "4.4.1" ], "description": "This entity implements a simple UART.", "license": "", "language": "vhdl-2008", "library": "olo", "source_url": "https://github.com/open-logic/open-logic.git", "tags": [ "asynchronous", "interface", "intf", "olo", "open", "receiver", "serial", "transmitter", "uart", "universal" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-03-10T06:51:30+01:00", "desc_source": "header", "external_uses": [ { "library": "work", "package": "en_cl_fix_pkg" }, { "library": "work", "package": "en_cl_fix_private_pkg" } ], "provides_packages": [ "olo_base_pkg_array", "olo_base_pkg_attribute", "olo_base_pkg_logic", "olo_base_pkg_math", "olo_base_pkg_string" ], "top_ports": { "olo_intf_uart": [ { "direction": "in", "name": "Clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Tx_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Tx_Ready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Tx_Data", "type": "std_logic_vector", "width": "DataBits_g - 1 downto 0" }, { "direction": "out", "name": "Rx_Valid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Rx_Data", "type": "std_logic_vector", "width": "DataBits_g - 1 downto 0" }, { "direction": "out", "name": "Rx_ParityError", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Uart_Tx", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Uart_Rx", "type": "std_logic", "width": "" } ] } }, { "namespace": "opencores", "name": "1000base-x", "latest": "master", "versions": [ "master" ], "description": "1000BASE-X physical coding sublayer (PCS) implementing IEEE 802.3 8b/10b encoding and synchronization for SFP-attached 1G optical transceivers.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": 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"" } ] }, "top_modules": [ "ge_1000baseX_test" ] }, { "namespace": "opencores", "name": "6809_6309_compatible_core", "latest": "master", "versions": [ "master" ], "description": "Motorola 6809 / Hitachi 6309 8/16-bit hybrid processor compatible with both ISAs, 16-bit address space, dual accumulator.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/6809_6309_compatible_core.git", "tags": [ "alu", "calc", "cpu", "decode", "ea", "mc6809", "op", "processor" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T23:52:00Z", "updated_at": "2014-07-07T03:57:00+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "top_ports": { "MC6809_cpu": [ { "direction": "in", "name": "cpu_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "cpu_reset", "type": "wire", "width": "" }, { "direction": "in", "name": "cpu_nmi_n", "type": "wire", "width": "" }, { "direction": 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{ "direction": "out", "name": "path_left_addr_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "path_right_addr_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "dest_reg_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "path_left_addr_lo", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "path_right_addr_lo", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "dest_reg_lo", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "write_dest", "type": "wire", "width": "" }, { "direction": "out", "name": "source_size", "type": "wire", "width": "" }, { "direction": "out", "name": "result_size", "type": "wire", "width": "" }, { "direction": "out", "name": "mode", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "optype", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "use_s", "type": "wire", "width": "" }, { "direction": "in", "name": "eapostbyte", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "noofs", "type": "wire", "width": "" }, { "direction": "out", "name": "ofs8", "type": "wire", "width": "" }, { "direction": "out", "name": "ofs16", "type": "wire", "width": "" }, { "direction": "out", "name": "write_post", "type": "wire", "width": "" }, { "direction": "out", "name": "isind", "type": "wire", "width": "" }, { "direction": "out", "name": "alu_opcode", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "dec_alu_right_path_mod", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "dest_flags", "type": "wire", "width": "" }, { "direction": "in", "name": "CCR", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "cond_taken", "type": "wire", "width": "" } ], "logic8": [ { "direction": "in", "name": "clk_in", "type": "wire", "width": "" }, { "direction": "in", "name": "a_in", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "b_in", "type": "wire", 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"wire", "width": "" }, { "direction": "out", "name": "half_c_out", "type": "wire", "width": "" }, { "direction": "in", "name": "overflow_in", "type": "wire", "width": "" }, { "direction": "in", "name": "q_mul_in", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "b", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "q", "type": "wire", "width": "[15:0]" } ], "regblock": [ { "direction": "in", "name": "clk_in", "type": "wire", "width": "" }, { "direction": "in", "name": "path_left_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "path_right_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "write_reg_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "exg_dest_r", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "eapostbyte", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "offset16", 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"[3:0]" }, { "direction": "out", "name": "operand2", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand2_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "address", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "address_type", "type": "wire", "width": "" }, { "direction": "in", "name": "address_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "movem_modreg", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "movem_modreg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "movem_loop", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "movem_loop_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "movem_reg", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "movem_reg_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ir", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "ir_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "pc", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "trap_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "offset", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "offset_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "index", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "index_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "stop_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "stop_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "trace_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "trace_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "group_0_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "group_0_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "instruction_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "instruction_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "read_modify_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_reset_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_interrupt_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_read_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_blocked_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "data_write", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "data_write_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_address", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "An_address_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_input_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "Dn_address", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "Dn_address_control", "type": "wire", "width": "" }, { "direction": "in", "name": "decoder_alu", "type": "wire", "width": "[17:0]" }, { "direction": "out", "name": "decoder_alu_reg", "type": "wire", "width": "[17:0]" }, { "direction": "in", "name": "An_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "micro_pc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "micro_data", "type": "wire", "width": "[87:0]" }, { "direction": "in", "name": "the", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor", "type": "wire", "width": "" }, { "direction": "out", "name": "decoder_micropc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "save_ea", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_write", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_read", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "load_ea", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "cond", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ccr", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "condition", "type": "wire", "width": "" }, { "direction": "in", "name": "alu_control", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "alu_signal", "type": "wire", "width": "" }, { "direction": "out", "name": "alu_mult_div_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "overflow", "type": "wire", "width": "" }, { "direction": "in", "name": "prefetch_ir_valid_32", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_address_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_bus_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "finished", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_control", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "branch_offset", "type": "wire", "width": "[3:0]" } ], "decoder": [ { "direction": "in", "name": "CLK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_n", "type": "wire", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "wire", "width": "[31:2]" }, { "direction": "out", "name": "DAT_O", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "DAT_I", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SEL_O", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_O", "type": "wire", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "SGL_O", "type": "wire", "width": "" }, { "direction": "out", "name": "BLK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "RMW_O", "type": "wire", "width": "" }, { "direction": "out", "name": "CTI_O", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "BTE_O", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fc_o", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ipl_i", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "reset_o", "type": "wire", "width": "" }, { "direction": "out", "name": "blocked_o", "type": "wire", "width": "" }, { "direction": "in", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ipm_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "address_type_i", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "data_write_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "data_read_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_change_i", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "prefetch_ir_o", "type": "wire", "width": "[79:0]" }, { "direction": "out", "name": "prefetch_ir_valid_32_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_80_o", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_i", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_address_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_bus_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "finished_o", "type": "wire", "width": "" }, { "direction": "out", "name": "interrupt_trap_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "interrupt_mask_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "rw_state_o", "type": "wire", "width": "" }, { "direction": "out", "name": "fc_state_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "fault_address_state_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clock", "type": "wire", "width": "" }, { "direction": "in", "name": "data_read", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "prefetch_ir", "type": "wire", "width": "[79:0]" }, { "direction": "in", "name": "prefetch_ir_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "sr", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "rw_state", "type": "wire", "width": "" }, { "direction": "in", "name": "fc_state", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "fault_address_state", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "interrupt_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "interrupt_mask", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "decoder_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "usp", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_output", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_output", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "pc_change", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ea_reg", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_reg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "ea_mod", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_mod_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ea_type", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ea_type_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand1_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand2", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand2_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "address", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "address_type", "type": "wire", "width": "" }, { "direction": "in", "name": "address_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "movem_modreg", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "movem_modreg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "movem_loop", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "movem_loop_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "movem_reg", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "movem_reg_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ir", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "ir_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "pc", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "trap_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "offset", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "offset_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "index", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "index_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "stop_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "stop_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "trace_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "trace_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "group_0_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "group_0_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "instruction_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "instruction_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "read_modify_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_reset_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_interrupt_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_read_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_blocked_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "data_write", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "data_write_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_address", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "An_address_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_input_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "Dn_address", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "Dn_address_control", "type": "wire", "width": "" }, { "direction": "in", "name": "decoder_alu", "type": "wire", "width": "[17:0]" }, { "direction": "out", "name": "decoder_alu_reg", "type": "wire", "width": "[17:0]" }, { "direction": "in", "name": "An_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "micro_pc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "micro_data", "type": "wire", "width": "[87:0]" }, { "direction": "in", "name": "the", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor", "type": "wire", "width": "" }, { "direction": "out", "name": "decoder_micropc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "save_ea", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_write", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_read", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "load_ea", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "cond", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ccr", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "condition", "type": "wire", "width": "" }, { "direction": "in", "name": "alu_control", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "alu_signal", "type": "wire", "width": "" }, { "direction": "out", "name": "alu_mult_div_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "overflow", "type": "wire", "width": "" }, { "direction": "in", "name": "prefetch_ir_valid_32", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_address_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_bus_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "finished", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_control", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "branch_offset", "type": "wire", "width": "[3:0]" } ], "memory_registers": [ { "direction": "in", "name": "CLK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_n", "type": "wire", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "wire", "width": "[31:2]" }, { "direction": "out", "name": "DAT_O", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "DAT_I", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SEL_O", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_O", "type": "wire", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "SGL_O", "type": "wire", "width": "" }, { "direction": "out", "name": "BLK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "RMW_O", "type": "wire", "width": "" }, { "direction": "out", "name": "CTI_O", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "BTE_O", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fc_o", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ipl_i", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "reset_o", "type": "wire", "width": "" }, { "direction": "out", "name": "blocked_o", "type": "wire", "width": "" }, { "direction": "in", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ipm_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "address_type_i", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "data_write_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "data_read_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_change_i", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "prefetch_ir_o", "type": "wire", "width": "[79:0]" }, { "direction": "out", "name": "prefetch_ir_valid_32_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_80_o", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_i", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_address_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_bus_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "finished_o", "type": "wire", "width": "" }, { "direction": "out", "name": "interrupt_trap_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "interrupt_mask_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "rw_state_o", "type": "wire", "width": "" }, { "direction": "out", "name": "fc_state_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "fault_address_state_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clock", "type": "wire", "width": "" }, { "direction": "in", "name": "data_read", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "prefetch_ir", "type": "wire", "width": "[79:0]" }, { "direction": "in", "name": "prefetch_ir_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "sr", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "rw_state", "type": "wire", "width": "" }, { "direction": "in", "name": "fc_state", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "fault_address_state", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "interrupt_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "interrupt_mask", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "decoder_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "usp", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_output", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_output", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "pc_change", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ea_reg", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_reg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "ea_mod", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_mod_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ea_type", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ea_type_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand1_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand2", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand2_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "address", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "address_type", "type": "wire", "width": "" }, { "direction": "in", "name": "address_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "movem_modreg", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "movem_modreg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "movem_loop", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "movem_loop_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "movem_reg", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "movem_reg_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ir", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "ir_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "pc", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "trap_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "offset", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "offset_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "index", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "index_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "stop_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "stop_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "trace_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "trace_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "group_0_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "group_0_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "instruction_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "instruction_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "read_modify_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_reset_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_interrupt_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_read_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_write_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "do_blocked_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "data_write", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "data_write_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_address", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "An_address_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "An_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_input_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "Dn_address", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "Dn_address_control", "type": "wire", "width": "" }, { "direction": "in", "name": "decoder_alu", "type": "wire", "width": "[17:0]" }, { "direction": "out", "name": "decoder_alu_reg", "type": "wire", "width": "[17:0]" }, { "direction": "in", "name": "An_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_input", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_write_enable", "type": "wire", "width": "" }, { "direction": "in", "name": "Dn_size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "micro_pc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "micro_data", "type": "wire", "width": "[87:0]" }, { "direction": "in", "name": "the", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor", "type": "wire", "width": "" }, { "direction": "out", "name": "decoder_micropc", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "save_ea", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_write", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "perform_ea_read", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "load_ea", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "cond", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ccr", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "condition", "type": "wire", "width": "" }, { "direction": "in", "name": "alu_control", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "alu_signal", "type": "wire", "width": "" }, { "direction": "out", "name": "alu_mult_div_ready", "type": "wire", "width": "" }, { "direction": "in", "name": "overflow", "type": "wire", "width": "" }, { "direction": "in", "name": "prefetch_ir_valid_32", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_address_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "jmp_bus_trap", "type": "wire", "width": "" }, { "direction": "in", "name": "finished", "type": "wire", "width": "" }, { "direction": "in", "name": "branch_control", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "branch_offset", "type": "wire", "width": "[3:0]" } ], "microcode_branch": [ { "direction": "in", "name": "CLK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_n", "type": "wire", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "wire", "width": "[31:2]" }, { "direction": "out", "name": "DAT_O", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "DAT_I", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SEL_O", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "STB_O", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_O", "type": "wire", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "wire", "width": "" }, { "direction": "in", "name": "ERR_I", "type": "wire", "width": "" }, { "direction": "in", "name": "RTY_I", "type": "wire", "width": "" }, { "direction": "out", "name": "SGL_O", "type": "wire", "width": "" }, { "direction": "out", "name": "BLK_O", "type": "wire", "width": "" }, { "direction": "out", "name": "RMW_O", "type": "wire", "width": "" }, { "direction": "out", "name": "CTI_O", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "BTE_O", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fc_o", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ipl_i", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "reset_o", "type": "wire", "width": "" }, { "direction": "out", "name": "blocked_o", "type": "wire", "width": "" }, { "direction": "in", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "supervisor_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ipm_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "address_type_i", "type": "wire", "width": "" }, { "direction": "in", "name": "read_modify_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "data_write_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "data_read_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_change_i", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "prefetch_ir_o", "type": "wire", "width": "[79:0]" }, { "direction": "out", "name": "prefetch_ir_valid_32_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "prefetch_ir_valid_80_o", "type": "wire", "width": "" }, { "direction": "in", "name": "do_reset_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_blocked_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_read_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_write_i", "type": "wire", "width": "" }, { "direction": "in", "name": "do_interrupt_i", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_address_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "jmp_bus_trap_o", "type": "wire", "width": "" }, { "direction": "out", "name": "finished_o", "type": "wire", "width": "" }, { "direction": "out", "name": "interrupt_trap_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "interrupt_mask_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "rw_state_o", "type": "wire", "width": "" }, { "direction": "out", "name": "fc_state_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "fault_address_state_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clock", "type": "wire", "width": "" }, { "direction": "in", "name": "data_read", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "prefetch_ir", "type": "wire", "width": "[79:0]" }, { "direction": "in", "name": "prefetch_ir_valid", "type": "wire", "width": "" }, { "direction": "in", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "sr", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "rw_state", "type": "wire", "width": "" }, { "direction": "in", "name": "fc_state", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "fault_address_state", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "interrupt_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "interrupt_mask", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "decoder_trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "usp", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "Dn_output", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "An_output", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "pc_change", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ea_reg", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_reg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "ea_mod", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ea_mod_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ea_type", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ea_type_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand1_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "operand2", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "operand2_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "address", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "address_type", "type": "wire", "width": "" }, { "direction": "in", "name": "address_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "size", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "size_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "movem_modreg", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "movem_modreg_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "movem_loop", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "movem_loop_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "movem_reg", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "movem_reg_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "ir", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "ir_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "pc", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "pc_control", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "trap", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "trap_control", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "offset", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "offset_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "index", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "index_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "stop_flag", "type": "wire", "width": "" }, { "direction": "in", "name": "stop_flag_control", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "trace_flag", "type": "wire", "width": "" }, { "direction": "in", "name": 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"in", "name": "clk4_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst5_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk5_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst6_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk6_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst7_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk7_i", "type": "wire", "width": "" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "select", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "clk_o", "type": "wire", "width": "" }, { "direction": "in", "name": "always", "type": "wire", "width": "" }, { "direction": "in", "name": "gclk0", "type": "wire", "width": "" } ], "debouncer": [ { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "button_i", "type": "wire", "width": "" }, { "direction": "out", "name": "button_o", "type": "wire", "width": "" }, { "direction": "in", "name": "button_2", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "default", "type": "wire", "width": "" } ], "oc_fifo_basic": [ { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "out", "name": "have", "type": "wire", "width": "" }, { "direction": "in", "name": "take", "type": "wire", "width": "" }, { "direction": "out", "name": "take_do", "type": "wire", "width": "[DW-1:0]" }, { "direction": "out", "name": "need", "type": "wire", "width": "" }, { "direction": "in", "name": "give", "type": "wire", "width": "" }, { "direction": "in", "name": "give_di", "type": "wire", "width": "[DW-1:0]" } ], "random_ff": [ { "direction": "out", "name": "DOES", "type": "wire", "width": "" }, { "direction": "in", "name": "D", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "out", "name": "Q", "type": "wire", "width": "" }, { "direction": "in", "name": "CLRN", "type": "wire", "width": "" }, { "direction": "in", "name": "SETN", "type": "wire", "width": "" }, { "direction": "in", "name": "SI", "type": "wire", "width": "" }, { "direction": "in", "name": "input", "type": "wire", "width": "" } ] }, "top_modules": [ "arbiter", "bc_fifo_basic", "clock_detect", "clock_switch2_basic", "clock_switch3_basic", "clock_switch4_basic", "clock_switch8_basic", "debouncer", "oc_fifo_basic", "random_ff" ] }, { "namespace": "opencores", "name": "cdc_ufifo", "latest": "master", "versions": [ "master" ], "description": "cdc_ufifo generate an minimalist fifo. it can be 4 cells minimum. by default used implementation without ram only standart cells used , and it can be selected if need. most slowest stage is the output multiplexor.", "license": "Apache-2.0", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/cdc_ufifo.git", "tags": [ "cdc", "clock", "crossing", "delay", "dffe", "domain", "ff", "prim", "pulse", "ufifo" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T10:26:01Z", "updated_at": "2010-12-02T13:30:18+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "header", "top_ports": { "cdc_ufifo": [ { "direction": "out", "name": "multiplexor", "type": "wire", "width": "" }, { "direction": "out", "name": "or", "type": "wire", "width": "" }, { "direction": "in", "name": "in_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "[lpm_width-1:0]" }, { "direction": "out", "name": "q", "type": "wire", "width": "[lpm_width-1:0]" }, { "direction": "out", "name": "ready", "type": "wire", "width": "" } ], "gray2bin": [ { "direction": "out", "name": "bin", "type": "wire", "width": "[lpm_size-1:0]" }, { "direction": "in", "name": "gray", "type": "wire", "width": "[lpm_size-1:0]" } ] }, "top_modules": [ "cdc_ufifo", "gray2bin" ] }, { "namespace": "opencores", "name": "cfi_ctrl", "latest": "master", "versions": [ "master" ], "description": "Top level of CFI controller with 32-bit Wishbone classic interface Intended to be used at about 66MHz with a 32MB CFI flash part with 16-bit data interface.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/cfi_ctrl.git", "tags": [ "cfi", "control", "controller", "ctrl", "engine" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T10:26:01Z", "updated_at": "2011-10-23T12:05:51+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "header", "top_ports": { "cfi_ctrl": [ { "direction": "inout", "name": "flash_dq_io", "type": "wire", "width": "[flash_dq_width-1:0]" }, { "direction": "out", "name": "flash_adr_o", "type": "wire", "width": "[flash_adr_width-1:0]" }, { "direction": "out", "name": "flash_adv_n_o", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_ce_n_o", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_clk_o", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_oe_n_o", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_rst_n_o", "type": "wire", "width": "" }, { "direction": "in", "name": "flash_wait_i", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_we_n_o", "type": "wire", "width": "" }, { "direction": "out", "name": "flash_wp_n_o", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_err_o", "type": "wire", "width": "" } ] }, "top_modules": [ "cfi_ctrl" ] }, { "namespace": "opencores", "name": "copyblaze", "latest": "master", "versions": [ "master" ], "description": "PicoBlaze-compatible 8-bit microcontroller in VHDL-2008 (Adrien Trousson 2015+). Compact softcore with peripheral ecosystem (UART, GPIO) over Wishbone.", "license": "LGPL-2.1-only", "language": "vhdl-2008", "library": "work", "source_url": "https://github.com/freecores/copyblaze.git", "tags": [ "asynchronous", "bancregister", "copyblaze", "decodecontrol", "ecosystem", "fulladder", "interrupt", "programcounter", "programflowcontrol", "scratchpad", "transmitter", "universal" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T22:57:14Z", "updated_at": "2011-12-25T11:08:26+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "provides_packages": [ "Usefull_Pkg" ], "top_ports": { "WBOPRT08": [ { "direction": "out", "name": "ACK_O", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "CLK_I", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "DAT_I", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "DAT_O", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "RST_I", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "STB_I", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "WE_I", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "PRT_O", "type": "std_ulogic_vector", "width": "7 downto 0" } ], "cp_copyBlaze_ecoSystem": [ { "direction": "in", "name": "Clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "Interrupt_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "Interrupt_Ack_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "IN_PORT_i", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "OUT_PORT_o", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "PORT_ID_o", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "READ_STROBE_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "WRITE_STROBE_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "Freeze_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "in", "name": "DAT_I", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "DAT_O", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "WE_O", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "SEL_O", "type": "std_ulogic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "STB_O", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "std_ulogic", "width": "" } ], "mux32": [ { "direction": "in", "name": "input", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "output", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sel", "type": "std_logic_vector", "width": "4 downto 0" } ], "sp_ram": [ { "direction": "in", "name": "clka", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wea", "type": "std_logic_vector", "width": "0 downto 0" }, { "direction": "in", "name": "addra", "type": "std_logic_vector", "width": "addr_width-1 downto 0" }, { "direction": "in", "name": "dina", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "douta", "type": "std_logic_vector", "width": "data_width-1 downto 0" } ], "wb_Np_ram": [ { "direction": "in", "name": "wb_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb1_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb1_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb1_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb1_adr_i", "type": "std_logic_vector", "width": "addr_width-1 downto 0" }, { "direction": "in", "name": "wb1_dat_i", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb1_dat_o", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb1_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb2_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb2_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb2_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb2_adr_i", "type": "std_logic_vector", "width": "addr_width-1 downto 0" }, { "direction": "in", "name": "wb2_dat_i", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb2_dat_o", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb2_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb3_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb3_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb3_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb3_adr_i", "type": "std_logic_vector", "width": "addr_width-1 downto 0" }, { "direction": "in", "name": "wb3_dat_i", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb3_dat_o", "type": "std_logic_vector", "width": "data_width-1 downto 0" }, { "direction": "out", "name": "wb3_ack_o", "type": "std_logic", "width": "" } ], "wb_gpio": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "iport", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "oport", "type": "std_logic_vector", "width": "31 downto 0" } ], "wb_gpio_08": [ { "direction": "in", "name": "clk", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "iport", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "oport", "type": "std_ulogic_vector", "width": "7 downto 0" } ], "wb_scope": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_irq_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "probe", "type": "std_logic_vector", "width": "31 downto 0" } ], "wb_sram": [ { "direction": "in", "name": "clk", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_ulogic_vector", "width": "GEN_WIDTH_DATA-1 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_ulogic", "width": "" } ], "wb_timer": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_irq0_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_irq1_o", "type": "std_logic", "width": "" } ], "wb_timer_8": [ { "direction": "in", "name": "clk", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_ulogic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_irq0_o", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "wb_irq1_o", "type": "std_ulogic", "width": "" } ], "wb_uart": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 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GPL-3+ VHDL. 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"[`WIDTH:0]" }, { "direction": "in", "name": "zero2", "type": "wire", "width": "" } ], "point_scalar_mult": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "in", "name": "zero1", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "[`SCALAR_WIDTH:0]" }, { "direction": "out", "name": "done", "type": "wire", "width": "" }, { "direction": "out", "name": "x3", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "zero3", "type": "wire", "width": "" }, { "direction": "in", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "x2", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "in", "name": "zero2", "type": "wire", "width": "" } ] }, "top_modules": [ "f3_add1", "f3_mult", "f3_sub", "f3_sub1", "f3m_add3", "f3m_add4", "f3m_cubic", "f3m_inv", "f3m_mult", "f3m_mult3", "f3m_mux3", "f3m_mux6", "f3m_neg", "f3m_nine", "f3m_sub", "func1", "func10", "func11", "func2", "func3", "func4", "func5", "func7", "func8", "func9", "point_add", "point_scalar_mult" ] }, { "namespace": "opencores", "name": "ethernet_tri_mode", "latest": "master", "versions": [ "master" ], "description": "Tri-mode 10/100/1000 Mbps Ethernet MAC with GMII PHY interface (Jon Gao, OpenCores 2005-2018). 32-bit OpenCores streaming user bus, Wishbone-style CSR access, includes RMON statistics.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/ethernet_tri_mode.git", "tags": [ "access", "broadcast", "control", "controller", "cyclic", "physical", "receive", "receiver", "redundancy", "register", "transmit", "transmitter" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T22:57:14Z", "updated_at": "2009-01-08T13:53:34+00:00", "health_tier": "silver", "contract_url": "https://github.com/routertl/ip-index/blob/main/contracts/eth_mac_1g_requirements.yml", "test_status_url": "https://github.com/routertl/ip-index/blob/main/test_results/opencores/ethernet_tri_mode/last_run.json", "last_verified_at": "2026-05-06", "desc_source": "verdict", "contract": { "traits": { "back_to_back_rx_requires_rd_pulse": true, "requires_csr_init_before_tx": true, "rx_strips_fcs": true, "tx_hwmark_default_safe": false, "tx_user_frame_includes_fcs": false }, "defects": [ { "id": "OC-TRIMODE-TX-HWMARK", "severity": "critical", "kind": "underrun-on-low-hwmark", "discovered": "2026-05-03", "provenance": "RTL-T2", "evidence": "Tx_Hwmark default 9 entries; >512 B frames hit underrun before frame fully buffered, deliver as constant ~2,560 B GIANT wire frames regardless of input size. VCD-confirmed (Tx_en stays HIGH continuously through full 20.4-20.5 \u00b5s span) and lever-experiment-confirmed (HWM = 31 collapses 4 GIANTs to 0).", "recoverable": true, "workaround": "CSR-write Tx_Hwmark >= 31 entries (5'h1F) before any TX traffic", "fix_pr": null, "review_after": "2026-08-03" }, { "id": "OC-TRIMODE-RX-WAIT-END", "severity": "major", "kind": "protocol-handshake-mismatch", "discovered": "2026-05-03", "provenance": "RTL-T3", "evidence": "MAC_rx_FF.v SYS_wait_end \u2192 SYS_idle requires !Rx_mac_rd; perpetual-ready hosts (modern AXI-Stream-style ingress) wedge after frame 0 EOP and never receive subsequent frames. VCD-confirmed (FSM transitions from SYS_read \u2192 SYS_wait_end at first EOP and never moves again across 1.4 Mns sim).", "recoverable": true, "workaround": "BFM/host pulses Rx_mac_rd low for one cycle after each EOP", "fix_pr": null, "review_after": "2026-08-03" } ] }, "top_ports": { "MAC_top": [ { "direction": "in", "name": "Reset", "type": "wire", "width": "" }, { "direction": "in", "name": "Clk_125M", "type": "wire", "width": "" }, { "direction": "in", "name": "Clk_user", "type": "wire", "width": "" }, { "direction": "in", "name": "Clk_reg", "type": "wire", "width": "" }, { "direction": "out", "name": "Speed", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "Rx_mac_ra", "type": "wire", "width": "" }, { "direction": "in", "name": "Rx_mac_rd", "type": "wire", "width": "" }, { "direction": "out", "name": "Rx_mac_data", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "Rx_mac_BE", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": 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"wire", "width": "[5:0]" }, { "direction": "out", "name": "RX_MAX_LENGTH", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "RX_MIN_LENGTH", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "CPU_rd_addr", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "CPU_rd_apply", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_rd_grant", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_rd_dout", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "Line_loop_en", "type": "wire", "width": "" }, { "direction": "out", "name": "Speed", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "Divider", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "CtrlData", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "Rgad", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "Fiad", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": 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"in", "name": "rx_giga_mode", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_ctrl", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "tx_giga_mode", "type": "wire", "width": "" } ], "ha1588_axi": [ { "direction": "in", "name": "S_AXI_REG_ACLK", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_ARESETN", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_AWADDR", "type": "wire", "width": "[C_S_AXI_REG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_REG_AWPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "in", "name": "S_AXI_REG_AWVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_REG_AWREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_WDATA", "type": "wire", "width": "[C_S_AXI_REG_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_REG_WSTRB", "type": "wire", "width": "[C_S_AXI_REG_DATA_WIDTH/8-1:0]" }, { "direction": "in", "name": "S_AXI_REG_WVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_REG_WREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_REG_BRESP", "type": "wire", "width": "[2-1:0]" }, { "direction": "out", "name": "S_AXI_REG_BVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_BREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_ARADDR", "type": "wire", "width": "[C_S_AXI_REG_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_REG_ARPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "in", "name": "S_AXI_REG_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_REG_ARREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_REG_RDATA", "type": "wire", "width": "[C_S_AXI_REG_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "S_AXI_REG_RRESP", "type": "wire", "width": "[2-1:0]" }, { "direction": "out", "name": "S_AXI_REG_RVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_REG_RREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "Ports", "type": "wire", "width": "" }, { "direction": "out", "name": "INTR_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "rtc_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "rtc_time_ptp_ns", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rtc_time_ptp_sec", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "rtc_time_one_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_ctrl", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "rx_giga_mode", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_ctrl", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_data", "type": "wire", "width": "[ 7:0]" }, { "direction": "in", "name": "tx_giga_mode", "type": "wire", "width": "" } ], "ha1588_wb": [ { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "adr_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "rtc_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "rtc_time_ptp_ns", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rtc_time_ptp_sec", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "rtc_time_one_pps", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_ctrl", "type": "wire", "width": "" }, { "direction": "in", "name": "rx_gmii_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "rx_giga_mode", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_ctrl", "type": "wire", "width": "" }, { "direction": "in", "name": "tx_gmii_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "tx_giga_mode", "type": "wire", "width": "" } ] }, "top_modules": [ "ha1588_avl", "ha1588_axi", "ha1588_wb" ] }, { "namespace": "opencores", "name": "i2s_interface", "latest": "master", "versions": [ "master" ], "description": "I\u00b2S audio bus interface controller with Wishbone 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"direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_bte_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "wb_cti_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "ADDR_WIDTH - 1 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "DATA_WIDTH -1 downto 0" }, { "direction": "in", "name": "i2s_sd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "DATA_WIDTH - 1 downto 0" }, { "direction": "out", "name": "rx_int_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_sck_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_ws_o", "type": "std_logic", "width": "" } ], "rx_i2s_tops": [ { "direction": "in", "name": "wb_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_bte_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "wb_cti_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "ADDR_WIDTH - 1 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "DATA_WIDTH -1 downto 0" }, { "direction": "in", "name": "i2s_sd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2s_sck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2s_ws_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "DATA_WIDTH - 1 downto 0" }, { "direction": "out", "name": "rx_int_o", "type": "std_logic", "width": "" } ], "tx_i2s_topm": [ { "direction": "in", "name": "wb_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_bte_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "wb_cti_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "ADDR_WIDTH - 1 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "DATA_WIDTH -1 downto 0" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "DATA_WIDTH - 1 downto 0" }, { "direction": "out", "name": "tx_int_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_sd_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_sck_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_ws_o", "type": "std_logic", "width": "" } ], "tx_i2s_tops": [ { "direction": "in", "name": "wb_clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_bte_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "wb_cti_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "ADDR_WIDTH - 1 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "DATA_WIDTH -1 downto 0" }, { "direction": "in", "name": "i2s_sck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "i2s_ws_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "DATA_WIDTH - 1 downto 0" }, { "direction": "out", "name": "tx_int_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "i2s_sd_o", "type": "std_logic", "width": "" } ] }, "top_modules": [ "rx_i2s_topm", "rx_i2s_tops", "tx_i2s_topm", "tx_i2s_tops" ] }, { "namespace": "opencores", "name": "iicmb", "latest": "master", "versions": [ "master" ], "description": "I2C with interrupt support", "license": "BSD-2-Clause", "language": "vhdl-2008", "library": "iicmb", "source_url": "https://github.com/sshuv/iicmb.git", "tags": [ "av", "avalon", "bus", "conditioner", "iicmb", "mm", "multiplexer", "mux", "sq", "state", "wb", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2024-10-01T21:23:24+03:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "ports", "provides_packages": [ "iicmb_int_pkg", "iicmb_pkg" ], "top_ports": { "iicmb_m_av": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_rst", "type": "std_logic", "width": "" }, { "direction": "out", "name": "waitrequest", "type": "std_logic", "width": "" }, { "direction": "out", "name": "readdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "readdatavalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "writedata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "write", "type": "std_logic", "width": "" }, { "direction": "in", "name": "read", "type": "std_logic", "width": "" }, { "direction": "in", "name": "byteenable", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "irq", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "in", "name": "sda_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "scl_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "sda_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" } ], "iicmb_m_sq": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "s_rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cs_start", "type": "std_logic", "width": "" }, { "direction": "out", "name": "cs_busy", "type": "std_logic", "width": "" }, { "direction": "out", "name": "cs_status", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "scl_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "in", "name": "sda_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "scl_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "sda_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" } ], "iicmb_m_wb": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "stb_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ack_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "adr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dat_i", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "dat_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "irq", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "in", "name": "sda_i", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "scl_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" }, { "direction": "out", "name": "sda_o", "type": "std_logic_vector", "width": "0 to g_bus_num - 1" } ] }, "top_modules": [ "iicmb_m_av", "iicmb_m_sq", "iicmb_m_wb" ] }, { "namespace": "opencores", "name": "jpegencode", "latest": "master", "versions": [ "master" ], "description": "This is the top level module of the JPEG Encoder Core. This module takes the output from the fifo_out module and sends it to the ff_checker module to check for FF's in the bitstream.", "license": "OpenCores-Permissive-1.0", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/jpegencode.git", "tags": [ "buffer", "cbd", "checker", "crd", "fifo", "huff", "jpeg", "quantizer", "queue", "sync", "synchronizer", "synchronous" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T10:26:01Z", "updated_at": "2022-10-31T01:41:03+01:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "header", "top_ports": { "jpeg_top": [ { "direction": "out", "name": "from", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "end_of_file_signal", "type": "wire", "width": "" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "data_in", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "JPEG_bitstream", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "data_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "end_of_file_bitstream_count", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "eof_data_partial_ready", "type": "wire", "width": "" } ] }, "top_modules": [ "jpeg_top" ] }, { "namespace": "opencores", "name": "linkruncca", "latest": "dc0a13c4d755", "versions": [ "HEAD", "dc0a13c4d755" ], "description": "Detects connected components in pixel data stream and outputs bounding box coordinates.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/routertl-mirrors/linkruncca.git", "tags": [ "access", "accumulator", "buf", "equivalence", "feature", "filler", "holes", "memory", "random", "reader", "resolver", "table" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T11:46:13Z", "updated_at": "2026-05-05T12:54:46+02:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "LinkRunCCA": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "datavalid_out", "type": "wire", "width": "" }, { "direction": "out", "name": "reg", "type": "wire", "width": "" }, { "direction": "in", "name": "A", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "always", "type": "wire", "width": "" } ] }, "top_modules": [ "LinkRunCCA" ] }, { "namespace": "opencores", "name": "m32632", "latest": "3f7adf4b32ae", "versions": [ "3f7adf4b32ae", "HEAD" ], "description": "National Semiconductor NS32000-series 32-bit CPU implementation in Verilog (Udo M\u00f6ller). Maintained at RetroPM/m32632; LGPL-2.1.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/RetroPM/m32632.git", "tags": [ "addsub", "aligner", "config", "control", "counter", "datapath", "dcache", "divider", "gruppe", "icache", "register", "switch" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T11:46:13Z", "updated_at": "2024-08-02T14:57:07+01:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "verdict", "top_ports": { "DCACHE_SM": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "DCA_CONTROL": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "DEBUG_AE": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": 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"direction": "in", "name": "WR_REG", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_OP", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "COP_IN", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "TT_DP", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "OVF_BCD", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CLR_LSB", "type": "wire", "width": "" }, { "direction": "out", "name": "COP_GO", "type": "wire", "width": "" }, { "direction": "out", "name": "multiplexer", "type": "wire", "width": "" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "UP_DP", "type": "wire", "width": "" }, { "direction": "out", "name": "WREN_L", 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{ "direction": "out", "name": "OUT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CY_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DO_BCD", "type": "wire", "width": "" }, { "direction": "out", "name": "BCD_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "BCD_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "MAN1", "type": "wire", "width": "[20:0]" }, { "direction": "in", "name": "SRCFLAGS", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "SELECT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MAN2", "type": "wire", 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"out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" } ], "DFPU_MISC": [ { "direction": "in", "name": "START", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MEI", "type": "wire", "width": "" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSD_1", "type": "wire", "width": "[52:32]" }, { "direction": "out", "name": "LSD_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "LOAD_MSD", "type": "wire", "width": "" }, { "direction": "in", "name": "A_IN", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CY_IN", "type": "wire", "width": "" }, { "direction": "in", "name": "SUBP", "type": "wire", "width": "" }, { "direction": "out", "name": "OUT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CY_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", 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"name": "DIN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "NOT_DEI", "type": "wire", "width": "" }, { "direction": "in", "name": "EXTDATA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSB", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NULL", "type": "wire", "width": "" }, { "direction": "out", "name": "MINUS", "type": "wire", "width": "" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "DONE", "type": "wire", "width": "" }, { "direction": "out", "name": "DIVI_OUT", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "DVZ_TRAP", "type": "wire", "width": "" }, { "direction": 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}, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MAN2", "type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "MODE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "MRESULT", "type": "wire", "width": "[105:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "NOT_DEI", "type": "wire", "width": "" }, { "direction": "in", "name": "EXTDATA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSB", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NULL", "type": "wire", "width": "" }, { "direction": "out", "name": "MINUS", "type": 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"WREN_L", "type": "wire", "width": "" }, { "direction": "out", "name": "DP_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "DP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" } ], "DP_FPU": [ { "direction": "in", "name": "START", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MEI", "type": "wire", "width": "" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSD_1", "type": "wire", "width": "[52:32]" }, { "direction": "out", "name": "LSD_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "LOAD_MSD", "type": "wire", "width": "" }, { "direction": "in", "name": "A_IN", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CY_IN", "type": "wire", "width": "" }, { "direction": "in", "name": "SUBP", "type": "wire", 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"type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "MODE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "MRESULT", "type": "wire", "width": "[105:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "NOT_DEI", "type": "wire", "width": "" }, { "direction": "in", "name": "EXTDATA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSB", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NULL", "type": "wire", "width": "" }, { "direction": "out", "name": "MINUS", "type": "wire", "width": "" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "DONE", "type": "wire", "width": "" }, { "direction": "out", "name": "DIVI_OUT", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "DVZ_TRAP", "type": "wire", "width": "" }, { "direction": "out", "name": "DEI_OVF", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "word", "type": "wire", "width": "" }, { "direction": "in", "name": "FSR", "type": "wire", "width": "[8:3]" }, { "direction": "in", "name": "WR_REG", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_OP", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "COP_IN", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "TT_DP", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "OVF_BCD", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CLR_LSB", "type": "wire", "width": "" }, { "direction": "out", "name": "COP_GO", "type": "wire", "width": "" }, { "direction": "out", "name": "multiplexer", "type": "wire", "width": "" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "UP_DP", "type": "wire", "width": "" }, { "direction": "out", "name": "WREN_L", "type": "wire", "width": "" }, { "direction": "out", "name": "DP_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "DP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" } ], "DP_LOGIK": [ { "direction": "in", "name": "START", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MEI", "type": "wire", "width": "" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSD_1", "type": "wire", "width": "[52:32]" }, { "direction": "out", "name": "LSD_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "LOAD_MSD", "type": "wire", "width": "" }, { "direction": "in", "name": "A_IN", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CY_IN", "type": "wire", "width": "" }, { "direction": "in", "name": "SUBP", "type": "wire", "width": "" }, { "direction": "out", "name": "OUT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CY_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DO_BCD", "type": "wire", "width": "" }, { "direction": "out", "name": "BCD_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "BCD_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "MAN1", "type": "wire", "width": "[20:0]" }, { "direction": "in", "name": "SRCFLAGS", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "SELECT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MAN2", "type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "MODE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "MRESULT", "type": "wire", "width": "[105:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "NOT_DEI", "type": "wire", "width": "" }, { "direction": "in", "name": "EXTDATA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOUT", 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"[31:0]" }, { "direction": "out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" } ], "FFS_LOGIK": [ { "direction": "in", "name": "Data", "type": "wire", "width": "" }, { "direction": "in", "name": "AA", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MRESULT", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "MASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ROT", "type": "wire", "width": "" }, { "direction": "in", "name": "SIZE", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SH_VAL", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SH_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SH_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MASK_SEL", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "FLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "dataa", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "cin", "type": "wire", "width": "" }, { "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "in", "name": "bwd", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "cout", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SFP_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BMASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": 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"type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "I_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PSR", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "BMCODE", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "OV_FLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "ACB_ZERO", "type": "wire", "width": "" }, { "direction": "out", "name": "STRING", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "Multiplexer", "type": "wire", "width": "" } ], "FILTCMP": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", 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"ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "FP_STAT_REG": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "WRADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "PCMATCH", "type": "wire", "width": "" }, { "direction": "in", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "out", "name": "CFG", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "MCR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_SEL", "type": "wire", "width": "" }, { "direction": "out", "name": "IVAR", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "IVAR_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "CINV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "Y_INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "DSR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DBG_TRAPS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "LFSR", "type": "wire", "width": "" }, { "direction": "in", "name": "UP_SP", "type": "wire", "width": "" }, { "direction": "in", "name": "TT_SP", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "FSR", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "TWREN", "type": "wire", "width": "" }, { "direction": "out", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "out", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "DOWR", "type": "wire", "width": "" }, { "direction": "in", "name": "BYDIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "WMASKE", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SELI", "type": "wire", "width": "" } ], "ICACHE_SM": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[28:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "C_VALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "READ_I", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "HOLD", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "ENA_HK", "type": "wire", "width": "" }, { "direction": "out", "name": "NEWCVAL", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "KOLLISION", "type": "wire", "width": "" }, { "direction": "out", "name": "STOP_ICRD", "type": "wire", "width": "" }, { "direction": "out", "name": "RUN_ICRD", "type": "wire", "width": "" }, { "direction": "out", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "KILLADR", "type": "wire", "width": "[11:7]" }, { "direction": "out", "name": "ICTODC", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "STOP_CINV", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "PTE_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "out", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "out", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PTB", "type": "wire", "width": "" } ], "ILL_UNDEF": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_STAT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "in", "name": "ALSB", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "USED", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "IC_DIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IC_INIT", "type": "wire", "width": "" }, { "direction": "in", "name": "RESTART", "type": "wire", "width": "" }, { "direction": "in", "name": "STOP_IC", "type": "wire", "width": "" }, { "direction": "out", "name": "OPREG", "type": "wire", "width": "[55:0]" }, { "direction": "out", "name": "ANZ_VAL", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "IC_READ", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PC", "type": "wire", "width": "" }, { "direction": "out", "name": "NEXT_ADR", "type": "wire", "width": "" }, { "direction": "out", "name": "DATA_HOLD", "type": "wire", "width": "" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_TEX", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "INIT_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "LOAD_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "NEXT_PCA", "type": "wire", "width": "" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PC_NEW", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "in", "name": "ADIVAR", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_ICACHE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_SAVE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IC_USER", "type": "wire", "width": "" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "IPOS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "OPOS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "VALID", "type": "wire", "width": "" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ILL", "type": "wire", "width": "" }, { "direction": "out", "name": "UNDEF", "type": "wire", "width": "" }, { "direction": "in", "name": "PHASE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "SRC_1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "ADRD1", "type": "wire", "width": "[18:0]" }, { "direction": "in", "name": "PHRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "NXRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ACCA", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "OPERA", "type": "wire", "width": "[10:0]" }, { "direction": "out", "name": "STATE_0", "type": "wire", "width": "[66:0]" }, { "direction": "out", "name": "STATE_GROUP_50", "type": "wire", "width": "[66:0]" } ], "I_PFAD": [ { "direction": "in", "name": "Data", "type": "wire", "width": "" }, { "direction": "in", "name": "AA", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MRESULT", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "MASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ROT", "type": "wire", "width": "" }, { "direction": "in", "name": "SIZE", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SH_VAL", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SH_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SH_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MASK_SEL", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "FLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "dataa", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "cin", "type": "wire", "width": "" }, { "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "in", "name": "bwd", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "cout", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SFP_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BMASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "WRADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "RDAA", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "DETOIP", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "BITSEL", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "OVF_BCD", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "DSR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "I_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PSR", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "BMCODE", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "OV_FLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "ACB_ZERO", "type": "wire", "width": "" }, { "direction": "out", "name": "STRING", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "Multiplexer", "type": "wire", "width": "" } ], "KOLDETECT": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[28:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "C_VALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "READ_I", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "HOLD", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "ENA_HK", "type": "wire", "width": "" }, { "direction": "out", "name": "NEWCVAL", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "KOLLISION", "type": "wire", "width": "" }, { "direction": "out", "name": "STOP_ICRD", "type": "wire", "width": "" }, { "direction": "out", "name": "RUN_ICRD", "type": "wire", "width": "" }, { "direction": "out", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "KILLADR", "type": "wire", "width": "[11:7]" }, { "direction": "out", "name": "ICTODC", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "STOP_CINV", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "PTE_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "out", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "out", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PTB", "type": "wire", "width": "" } ], "M32632": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NMI_N", "type": "wire", "width": "" }, { "direction": "in", "name": "INT_N", "type": "wire", "width": "" }, { "direction": "out", "name": "STATUS", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "STATSIGS", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "IO_WR", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_RD", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_A", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IO_BE", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "IO_DI", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IO_Q", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "DC_INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_INHIBIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "IDRAM_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "DC_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "DC_WR", "type": "wire", "width": "" }, { "direction": "out", "name": "DRAM_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "DRAM_DI", "type": "wire", "width": "[35:0]" }, { "direction": "in", "name": "HOLD", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_AA", "type": "wire", "width": "[28:4]" }, { "direction": "out", "name": "COP_GO", "type": "wire", "width": "" }, { "direction": "out", "name": "COP_OP", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "COP_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_IN", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "Interface", "type": "wire", "width": "" } ], "MAKE_STAT": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "I_IOA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "I_IORD", "type": "wire", "width": "" }, { "direction": "in", "name": "D_IORD", "type": "wire", "width": "" }, { "direction": "in", "name": "D_IOBE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "GENSTAT", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ILO_SIG", "type": "wire", "width": "" }, { "direction": "in", "name": "DCWACC", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "IO_A", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IO_RD", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_BE", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "I_IORDY", "type": "wire", "width": "" }, { "direction": "out", "name": "D_IORDY", "type": "wire", "width": "" }, { "direction": "out", "name": "STATUS", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ILO", "type": "wire", "width": "" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_READ", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "KOLLISION", "type": "wire", "width": "" }, { "direction": "out", "name": "STATSIGS", "type": "wire", "width": "[7:0]" } ], "MMU_MATCH": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "MMU_UP": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "MULFILTER": [ { "direction": "in", "name": "Data", "type": "wire", "width": "" }, { "direction": "in", "name": "AA", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MRESULT", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "MASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ROT", "type": "wire", "width": "" }, { "direction": "in", "name": "SIZE", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SH_VAL", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SH_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SH_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MASK_SEL", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "FLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "dataa", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "cin", "type": "wire", "width": "" }, { "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "in", "name": "bwd", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "cout", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SFP_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BMASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "WRADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "RDAA", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "DETOIP", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "BITSEL", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "OVF_BCD", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "DSR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "I_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PSR", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "BMCODE", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "OV_FLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "ACB_ZERO", "type": "wire", "width": "" }, { "direction": "out", "name": "STRING", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "Multiplexer", "type": "wire", "width": "" } ], "NEU_VALID": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR_R", "type": "wire", "width": "[31:2]" }, { "direction": "in", "name": "MMU_Q", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW_PTB", "type": "wire", "width": "" }, { "direction": "in", "name": "PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "IVAR", "type": "wire", "width": "" }, { "direction": "in", "name": "WR_MRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "VADR", "type": "wire", "width": "[19:16]" }, { "direction": "in", "name": "MVALID", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "WE_MV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_MV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DAT_MV", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "NEW_PTB_RUN", "type": "wire", "width": "" }, { "direction": "in", "name": "CUPDATE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_ACC", "type": "wire", "width": "" }, { "direction": "in", "name": "CA_SET", "type": "wire", "width": "" }, { "direction": "in", "name": "HIT_ALL", "type": "wire", "width": "" }, { "direction": "in", "name": "UPDATE", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "INVAL_A", "type": "wire", "width": "" }, { "direction": "in", "name": "MDONE", "type": "wire", "width": "" }, { "direction": "in", "name": "USE_CA", "type": "wire", "width": "" }, { "direction": "in", "name": "INHIBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "KILL", "type": "wire", "width": "" }, { "direction": "out", "name": "WRCRAM0", "type": "wire", "width": "" }, { "direction": "out", "name": "WE_CV", "type": "wire", "width": "" }, { "direction": "out", "name": "WADR_CV", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DAT_CV", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "INIT_CA_RUN", "type": "wire", "width": "" }, { "direction": "out", "name": "WRSET0", "type": "wire", "width": "" }, { "direction": "in", "name": "RMW", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_FLAGS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "MMU_VA", "type": "wire", "width": "[31:16]" }, { "direction": "out", "name": "MMU_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "out", "name": "CI", "type": "wire", "width": "" }, { "direction": "in", "name": "CVALID", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DRAMSZ", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:4]" }, { "direction": "in", "name": "TAG0", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "INVAL_L", "type": "wire", "width": "" }, { "direction": "in", "name": "KDET", "type": "wire", "width": "" }, { "direction": "in", "name": "ENDRAM", "type": "wire", "width": "" }, { "direction": "in", "name": "DC_ILO", "type": "wire", "width": "" }, { "direction": "out", "name": "CA_HIT", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_SPACE", "type": "wire", "width": "" }, { "direction": "out", "name": "WB_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "ADR_EQU", "type": "wire", "width": "" }, { "direction": "out", "name": "TAGDAT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "IO_READY", "type": "wire", "width": "" }, { "direction": "in", "name": "CAPDAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "in", "name": "SEL_PTB1", "type": "wire", "width": "" }, { "direction": "in", "name": "CPU_OUT", "type": "wire", "width": "[28:12]" }, { "direction": "in", "name": "ENWR", "type": "wire", "width": "" }, { "direction": "in", "name": "IC_PREQ", "type": "wire", "width": "" }, { "direction": "in", "name": "DMA_CHK", "type": "wire", "width": "" }, { "direction": "in", "name": "ICTODC", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "RWVAL", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "QWATWO", "type": "wire", "width": "" }, { "direction": "out", "name": "IO_ACC", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_ADR", "type": "wire", "width": "[28:0]" }, { "direction": "out", "name": "PTE_DAT", "type": "wire", "width": "[19:0]" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IACC_STAT", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ABO_LEVEL1", "type": "wire", "width": "" }, { "direction": "out", "name": "AUX_DAT", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_ONE", "type": "wire", "width": "" }, { "direction": "out", "name": "MMU_DIN", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "IC_SIGS", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "KOMUX", "type": "wire", "width": "" }, { "direction": "out", "name": "DMA_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "HLDA", "type": "wire", "width": "" }, { "direction": "out", "name": "RWVFLAG", "type": "wire", "width": "" }, { "direction": "out", "name": "PTE_STAT", "type": "wire", "width": "[1:0]" } ], "OPDEC_REG": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_STAT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "in", "name": "ALSB", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "USED", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "IC_DIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IC_INIT", "type": "wire", "width": "" }, { "direction": "in", "name": "RESTART", "type": "wire", "width": "" }, { "direction": "in", "name": "STOP_IC", "type": "wire", "width": "" }, { "direction": "out", "name": "OPREG", "type": "wire", "width": "[55:0]" }, { "direction": "out", "name": "ANZ_VAL", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "IC_READ", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PC", "type": "wire", "width": "" }, { "direction": "out", "name": "NEXT_ADR", "type": "wire", "width": "" }, { "direction": "out", "name": "DATA_HOLD", "type": "wire", "width": "" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_TEX", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "INIT_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "LOAD_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "NEXT_PCA", "type": "wire", "width": "" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PC_NEW", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "in", "name": "ADIVAR", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_ICACHE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_SAVE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IC_USER", "type": "wire", "width": "" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "IPOS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "OPOS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "VALID", "type": "wire", "width": "" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ILL", "type": "wire", "width": "" }, { "direction": "out", "name": "UNDEF", "type": "wire", "width": "" }, { "direction": "in", "name": "PHASE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "SRC_1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "ADRD1", "type": "wire", "width": "[18:0]" }, { "direction": "in", "name": "PHRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "NXRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ACCA", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "OPERA", "type": "wire", "width": "[10:0]" }, { "direction": "out", "name": "STATE_0", "type": "wire", "width": "[66:0]" }, { "direction": "out", "name": "STATE_GROUP_50", "type": "wire", "width": "[66:0]" } ], "PREPDATA": [ { "direction": "in", "name": "START", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MEI", "type": "wire", "width": "" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSD_1", "type": "wire", "width": "[52:32]" }, { "direction": "out", "name": "LSD_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "LOAD_MSD", "type": "wire", "width": "" }, { "direction": "in", "name": "A_IN", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CY_IN", "type": "wire", "width": "" }, { "direction": "in", "name": "SUBP", "type": "wire", "width": "" }, { "direction": "out", "name": "OUT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CY_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DO_BCD", "type": "wire", "width": "" }, { "direction": "out", "name": "BCD_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "BCD_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "MAN1", "type": "wire", "width": "[20:0]" }, { "direction": "in", "name": "SRCFLAGS", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "SELECT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MAN2", "type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "MODE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "MRESULT", "type": "wire", "width": "[105:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MBIT", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "NOT_DEI", "type": "wire", "width": "" }, { "direction": "in", "name": "EXTDATA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSB", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NULL", "type": "wire", "width": "" }, { "direction": "out", "name": "MINUS", "type": "wire", "width": "" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "DONE", "type": "wire", "width": "" }, { "direction": "out", "name": "DIVI_OUT", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "DVZ_TRAP", "type": "wire", "width": "" }, { "direction": "out", "name": "DEI_OVF", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "word", "type": "wire", "width": "" }, { "direction": "in", "name": "FSR", "type": "wire", "width": "[8:3]" }, { "direction": "in", "name": "WR_REG", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "COP_OP", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "COP_IN", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "TT_DP", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "OVF_BCD", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CLR_LSB", "type": "wire", "width": "" }, { "direction": "out", "name": "COP_GO", "type": "wire", "width": "" }, { "direction": "out", "name": "multiplexer", "type": "wire", "width": "" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "UP_DP", "type": "wire", "width": "" }, { "direction": "out", "name": "WREN_L", "type": "wire", "width": "" }, { "direction": "out", "name": "DP_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "DP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "COP_OUT", "type": "wire", "width": "[127:0]" } ], "PROG_COUNTER": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_STAT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "in", "name": "ALSB", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "USED", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "IC_DIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IC_INIT", "type": "wire", "width": "" }, { "direction": "in", "name": "RESTART", "type": "wire", "width": "" }, { "direction": "in", "name": "STOP_IC", "type": "wire", "width": "" }, { "direction": "out", "name": "OPREG", "type": "wire", "width": "[55:0]" }, { "direction": "out", "name": "ANZ_VAL", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "IC_READ", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PC", "type": "wire", "width": "" }, { "direction": "out", "name": "NEXT_ADR", "type": "wire", "width": "" }, { "direction": "out", "name": "DATA_HOLD", "type": "wire", "width": "" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_TEX", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "INIT_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "LOAD_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "NEXT_PCA", "type": "wire", "width": "" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PC_NEW", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "in", "name": "ADIVAR", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_ICACHE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_SAVE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IC_USER", "type": "wire", "width": "" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "IPOS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "OPOS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "VALID", "type": "wire", "width": "" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ILL", "type": "wire", "width": "" }, { "direction": "out", "name": "UNDEF", "type": "wire", "width": "" }, { "direction": "in", "name": "PHASE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "SRC_1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "ADRD1", "type": "wire", "width": "[18:0]" }, { "direction": "in", "name": "PHRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "NXRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ACCA", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "OPERA", "type": "wire", "width": "[10:0]" }, { "direction": "out", "name": "STATE_0", "type": "wire", "width": "[66:0]" }, { "direction": "out", "name": "STATE_GROUP_50", "type": "wire", "width": "[66:0]" } ], "REGISTER": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "WRADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "PCMATCH", "type": "wire", "width": "" }, { "direction": "in", "name": "DBG_HIT", "type": "wire", "width": "" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "out", "name": "CFG", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "MCR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PTB_WR", "type": "wire", "width": "" }, { "direction": "out", "name": "PTB_SEL", "type": "wire", "width": "" }, { "direction": "out", "name": "IVAR", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "IVAR_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "CINV", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "Y_INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "DSR", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "DBG_TRAPS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "LFSR", "type": "wire", "width": "" }, { "direction": "in", "name": "UP_SP", "type": "wire", "width": "" }, { "direction": "in", "name": "TT_SP", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "FSR", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "TWREN", "type": "wire", "width": "" }, { "direction": "out", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "out", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "DOWR", "type": "wire", "width": "" }, { "direction": "in", "name": "BYDIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "WMASKE", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SELI", "type": "wire", "width": "" } ], "REG_LIST": [ { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "NEW", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_STAT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "PROT_ERROR", "type": "wire", "width": "" }, { "direction": "in", "name": "ALSB", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "USED", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "IC_DIN", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "IC_INIT", "type": "wire", "width": "" }, { "direction": "in", "name": "RESTART", "type": "wire", "width": "" }, { "direction": "in", "name": "STOP_IC", "type": "wire", "width": "" }, { "direction": "out", "name": "OPREG", "type": "wire", "width": "[55:0]" }, { "direction": "out", "name": "ANZ_VAL", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "IC_READ", "type": "wire", "width": "" }, { "direction": "out", "name": "NEW_PC", "type": "wire", "width": "" }, { "direction": "out", "name": "NEXT_ADR", "type": "wire", "width": "" }, { "direction": "out", "name": "DATA_HOLD", "type": "wire", "width": "" }, { "direction": "out", "name": "ABORT", "type": "wire", "width": "" }, { "direction": "out", "name": "IC_TEX", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "INIT_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "LOAD_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "NEXT_PCA", "type": "wire", "width": "" }, { "direction": "in", "name": "DISP", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "PC_NEW", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "SAVE_PC", "type": "wire", "width": "" }, { "direction": "in", "name": "FPU_TRAP", "type": "wire", "width": "" }, { "direction": "in", "name": "ADIVAR", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_ARCHI", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_ICACHE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "PC_SAVE", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "IC_USER", "type": "wire", "width": "" }, { "direction": "in", "name": "DIN", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "IPOS", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "INIT", "type": "wire", "width": "" }, { "direction": "out", "name": "OPOS", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "VALID", "type": "wire", "width": "" }, { "direction": "in", "name": "CFG", "type": "wire", "width": "[3:1]" }, { "direction": "out", "name": "ILL", "type": "wire", "width": "" }, { "direction": "out", "name": "UNDEF", "type": "wire", "width": "" }, { "direction": "in", "name": "PHASE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "SRC_1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "ADRD1", "type": "wire", "width": "[18:0]" }, { "direction": "in", "name": "PHRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "NXRD1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ACCA", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "OPERA", "type": "wire", "width": "[10:0]" }, { "direction": "out", "name": "STATE_0", "type": "wire", "width": "[66:0]" }, { "direction": "out", "name": "STATE_GROUP_50", "type": "wire", "width": "[66:0]" } ], "SCANDIG": [ { "direction": "in", "name": "START", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "MEI", "type": "wire", "width": "" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MSD_1", "type": "wire", "width": "[52:32]" }, { "direction": "out", "name": "LSD_1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "LOAD_MSD", "type": "wire", "width": "" }, { "direction": "in", "name": "A_IN", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CY_IN", "type": "wire", "width": "" }, { "direction": "in", "name": "SUBP", "type": "wire", "width": "" }, { "direction": "out", "name": "OUT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "CY_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "BRESET", "type": "wire", "width": "" }, { "direction": "in", "name": "DO_BCD", "type": "wire", "width": "" }, { "direction": "out", "name": "BCD_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "BCD_DONE", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "MAN1", "type": "wire", "width": "[20:0]" }, { "direction": "in", "name": "SRCFLAGS", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "SELECT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": 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"direction": "in", "name": "cin", "type": "wire", "width": "" }, { "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "in", "name": "bwd", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "cout", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SFP_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BMASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "LD_OUT", "type": "wire", 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{ "direction": "out", "name": "FP_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "TT_SP", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "SP_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "UP_SP", "type": "wire", "width": "" }, { "direction": "out", "name": "multiplexer", "type": "wire", "width": "" } ], "SHIFTER": [ { "direction": "in", "name": "Data", "type": "wire", "width": "" }, { "direction": "in", "name": "AA", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DOUT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MRESULT", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "MASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ROT", "type": "wire", "width": "" }, { "direction": "in", "name": "SIZE", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SH_VAL", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "SH_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "SH_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "MASK_SEL", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC2", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "FLAG", "type": "wire", "width": "" }, { "direction": "in", "name": "dataa", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "cin", "type": "wire", "width": "" }, { "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "in", "name": "bwd", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "result", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "cout", "type": "wire", "width": "" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SFP_DAT", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "BMASKE", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ADDR", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "in", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "DP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "LD_OUT", "type": "wire", "width": "" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "WRADR", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "RDAA", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "DETOIP", "type": "wire", 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{ "direction": "in", "name": "add_sub", "type": "wire", "width": "" }, { "direction": "out", "name": "result", "type": "wire", "width": "[35:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "SRC1", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "NZEXP", "type": "wire", "width": "[2:1]" }, { "direction": "in", "name": "BWD", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "SELECT", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "OUT", "type": "wire", "width": "[36:0]" }, { "direction": "out", "name": "IOUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "CMPRES", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "START", "type": "wire", "width": "" }, { "direction": "in", "name": "OPCODE", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "FSR", "type": "wire", "width": "[8:3]" }, { "direction": "in", "name": "FL", "type": "wire", "width": "" }, { "direction": "out", "name": "FP_OUT", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "TT_SP", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "SP_CMP", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "SP_MUX", "type": "wire", "width": "" }, { "direction": "out", "name": "UP_SP", "type": "wire", "width": "" }, { "direction": "out", "name": "multiplexer", "type": "wire", "width": "" } ], "WRPORT": [ { "direction": "in", "name": "WRITE", "type": "wire", "width": "" }, { "direction": "in", "name": "DRAM_Q", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "WRDATA", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "ENBYTE", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "VADDR", "type": "wire", "width": "[3:2]" }, { "direction": "in", "name": "DADDR", "type": "wire", "width": "[3:2]" }, { "direction": "out", "name": "WDAT", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "CAP_Q", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "ENB", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "BCLK", "type": "wire", "width": "" }, { "direction": "in", "name": "VALIN", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "WADR", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "WREN", "type": "wire", "width": "" }, { "direction": "in", "name": "RADR", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "VALOUT", "type": "wire", "width": "[23:0]" }, { "direction": "in", "name": "DBG_IN", "type": "wire", "width": "[40:2]" }, { "direction": "in", "name": "READ", "type": "wire", "width": "" }, { "direction": "in", "name": "USER", "type": "wire", "width": "" }, { "direction": "in", "name": "VIRTUELL", "type": "wire", "width": "" }, { "direction": "in", "name": "ACC_OK", "type": "wire", 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"name": "i6_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i6_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i7_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i7_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i7_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i7_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i7_wb_err_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t0_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t0_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t0_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t0_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t0_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t1_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t1_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t1_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t1_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t1_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t2_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t2_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t2_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t2_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t2_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t3_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t3_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t3_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t3_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t3_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t4_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t4_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t4_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t4_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t4_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t5_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t5_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t5_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t5_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t5_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t6_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t6_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t6_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t6_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t6_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t7_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t7_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t7_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t7_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t7_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t7_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t7_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t7_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t7_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t8_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t8_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t8_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t8_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t8_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t8_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t8_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t8_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t8_wb_err_i", "type": "wire", "width": "" } ], "tc_si_to_mt": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i0_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i0_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i0_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i0_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i0_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i0_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i0_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i0_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i0_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i1_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i1_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i1_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i1_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i1_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i1_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i1_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i1_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i1_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i2_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i2_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i2_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i2_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i2_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i2_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i2_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i2_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i2_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i3_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i3_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i3_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i3_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i3_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i3_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i3_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i3_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i3_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i4_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i4_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i4_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i4_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i4_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i4_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i4_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i4_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i4_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i5_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i5_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i5_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i5_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i5_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i5_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i5_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i5_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i5_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i6_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i6_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i6_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i6_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i6_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i6_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i6_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i6_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i6_wb_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_adr_i", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "in", "name": "i7_wb_sel_i", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "in", "name": "i7_wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "i7_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i7_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "out", "name": "i7_wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "i7_wb_err_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t0_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t0_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t0_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t0_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t0_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t0_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t1_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t1_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t1_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t1_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t1_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t1_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t2_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t2_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t2_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t2_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t2_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t2_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t3_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t3_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t3_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t3_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t3_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t3_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t4_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t4_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t4_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t4_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t4_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t4_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_adr_o", "type": "wire", "width": "[`TC_AW-1:0]" }, { "direction": "out", "name": "t5_wb_sel_o", "type": "wire", "width": "[`TC_BSW-1:0]" }, { "direction": "out", "name": "t5_wb_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t5_wb_dat_o", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t5_wb_dat_i", "type": "wire", "width": "[`TC_DW-1:0]" }, { "direction": "in", "name": "t5_wb_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "t5_wb_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "t6_wb_stb_o", "type": "wire", "width": "" }, { "direction": "out", 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"width": "[1:0]" }, { "direction": "in", "name": "b", "type": "wire", "width": "[5:0]" } ], "second_part": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "[`W6:0]" }, { "direction": "out", "name": "c", "type": "wire", "width": "[`W6:0]" }, { "direction": "out", "name": "done", "type": "wire", "width": "" }, { "direction": "in", "name": "ins2", "type": "wire", "width": "" }, { "direction": "in", "name": "f32m_mult", "type": "wire", "width": "" } ], "tate_pairing": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "xp", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "done", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[`W6:0]" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[`WIDTH:0]" } ] }, "top_modules": [ "duursma_lee_algo", "f32m_add3", "f32m_add4", "f32m_cubic", "f32m_mult", "f32m_mux6", "f32m_neg", "f32m_sub", "f33m_inv", "f33m_mult", "f33m_mult2", "f33m_mult3", "f33m_mux2", "f33m_mux3", "f33m_neg", "f36m_mult", "f3_add1", "f3_mult", "f3_sub", "f3_sub1", "f3m_add3", "f3m_add4", "f3m_cubic", "f3m_inv", "f3m_mult", "f3m_mult3", "f3m_mux3", "f3m_mux6", "f3m_neg", "f3m_nine", "f3m_sub", "func1", "func2", "func3", "func4", "func5", "func7", "func8", "second_part", "tate_pairing" ] }, { "namespace": "opencores", "name": "pci", "latest": "master", "versions": [ "master" ], "description": "Bidirectional 32-bit PCI \u2194 Wishbone bridge supporting both initiator and target operation (Tadej Markovic + Miha Dolenc, OpenCores 2001-2006).", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/pci.git", "tags": [ "asynchronous", "bridge32", "control", "controller", "interface", "master32", "multiplexer", "register", "synchronizer", "synchronous", "target32", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T22:57:14Z", "updated_at": "2009-03-10T08:24:20+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "top_ports": { "pci_bridge32": [ { "direction": "out", "name": "enables", "type": "wire", "width": "" }, { "direction": "out", "name": "with", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_rst_o", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_int_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_int_o", "type": "wire", "width": "" }, { "direction": "in", "name": "wbs_adr_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wbs_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wbs_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wbs_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wbs_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wbs_stb_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wbs_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wbs_cti_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wbs_bte_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "wbs_cab_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wbs_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbs_rty_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbs_err_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wbm_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wbm_dat_o", "type": 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"direction": "in", "name": "a", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": 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"type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", 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{ "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", "type": "wire", "width": "" }, { "direction": "out", "name": "q_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mux", "type": "wire", "width": "" }, { "direction": "out", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "sd", "type": "wire", "width": "" }, { "direction": "out", "name": "sum", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ], "bw_mckbuf_4p5x": [ { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", "type": "wire", "width": "" }, { "direction": "out", "name": "q_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mux", "type": "wire", "width": "" }, { "direction": "out", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "sd", "type": "wire", "width": "" }, { "direction": "out", "name": "sum", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ], "bw_mckbuf_6x": [ { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", "type": "wire", "width": "" }, { "direction": "out", "name": "q_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mux", "type": "wire", "width": "" }, { "direction": "out", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "sd", "type": "wire", "width": "" }, { "direction": "out", "name": "sum", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ], "bw_mckbuf_7x": [ { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", "type": "wire", "width": "" }, { "direction": "out", "name": "q_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mux", "type": "wire", "width": "" }, { "direction": "out", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "sd", "type": "wire", "width": "" }, { "direction": "out", "name": "sum", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ], "bw_mckbuf_8x": [ { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "" }, { "direction": "in", "name": "c", "type": "wire", "width": "" }, { "direction": "in", "name": "d", "type": "wire", "width": "" }, { "direction": "in", "name": "b1", "type": "wire", "width": "" }, { "direction": "in", "name": "b2", "type": "wire", "width": "" }, { "direction": "in", "name": "a1", "type": "wire", "width": "" }, { "direction": "in", "name": "a2", "type": "wire", "width": "" }, { "direction": "in", "name": "c1", "type": "wire", "width": "" }, { "direction": "in", "name": "c2", "type": "wire", "width": "" }, { "direction": "in", "name": "b3", "type": "wire", "width": "" }, { "direction": "in", "name": "a3", "type": "wire", "width": "" }, { "direction": "in", "name": "c3", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "d1", "type": "wire", "width": "" }, { "direction": "in", "name": "d2", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "" }, { "direction": "in", "name": "ck", "type": "wire", "width": "" }, { "direction": "out", "name": "module", "type": "wire", "width": "" }, { "direction": "out", "name": "q_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mux", "type": "wire", "width": "" }, { "direction": "out", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "sd", "type": "wire", "width": "" }, { "direction": "out", "name": "sum", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ], "bw_r_idct_array": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "index0_x", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "index1_x", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "index_sel_x", "type": "wire", "width": "" }, { "direction": "in", "name": "dec_wrway_x", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rdreq_x", "type": "wire", "width": "" }, { "direction": "in", "name": "wrreq_x", "type": "wire", "width": "" }, { "direction": "in", "name": "wrtag_w0_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w1_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w2_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w3_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "rdtag_w0_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w1_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w2_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w3_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[32:0]" } ], "bw_r_irf_72_4x1_mux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrens", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "save", "type": "wire", "width": "" }, { "direction": "in", "name": "save_addr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "restore", "type": "wire", "width": "" }, { "direction": "in", "name": "restore_addr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "wr_data0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data3", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "rd_thread", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "sel", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "x0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x3", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "y", "type": "wire", "width": "[71:0]" } ], "bw_r_irf_core": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_tid_s2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_exu_rs1_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_rs2_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_rs3_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_ren1_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren2_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren3_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_wen_w", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_wen_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_rd_m", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ecl_irf_rd_g", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "byp_irf_rd_data_w", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "byp_irf_rd_data_w2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "ecl_irf_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ecl_irf_tid_g", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_old_lo_cwp_e", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "rml_irf_new_lo_cwp_e", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "rml_irf_old_e_cwp_e", "type": "wire", "width": "[2:1]" }, { "direction": "in", "name": "rml_irf_new_e_cwp_e", "type": "wire", "width": "[2:1]" }, { "direction": "in", "name": "rml_irf_swap_even_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_swap_odd_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_swap_local_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_kill_restore_w", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_cwpswap_tid_e", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_old_agp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_new_agp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_swap_global", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_global_tid", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "irf_byp_rs1_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs2_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3h_data_d_l", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren1_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren2_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren3_d", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_rs1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs2", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs3", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs3h", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "irf_byp_rs1_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs2_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3h_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en2", "type": "wire", "width": "" }, { "direction": "in", "name": "active_win_thr_rd_w_neg", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "active_win_thr_rd_w2_neg", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "thr_rd_w_neg", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rd_w2_neg", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "swap_global_d1_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_global_d2", "type": "wire", "width": "" }, { "direction": "in", "name": "global_tid_d1", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "global_tid_d2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "old_agp_d1", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "new_agp_d2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "swap_local_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_local_w", "type": "wire", "width": "" }, { "direction": "in", "name": "old_lo_cwp_m", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "new_lo_cwp_w", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "swap_even_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_even_w", "type": "wire", "width": "" }, { "direction": "in", "name": "old_e_cwp_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "new_e_cwp_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "swap_odd_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_odd_w", "type": "wire", "width": "" }, { "direction": "in", "name": "cwpswap_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cwpswap_tid_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "kill_restore_w", "type": "wire", "width": "" } ], "bw_r_irf_register": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrens", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "save", "type": "wire", "width": "" }, { "direction": "in", "name": "save_addr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "restore", "type": "wire", "width": "" }, { "direction": "in", "name": "restore_addr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "wr_data0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data3", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "rd_thread", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "sel", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "x0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x3", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "y", "type": "wire", "width": "[71:0]" } ], "bw_r_rf16x2": [ { "direction": "in", "name": "din", "type": "wire", "width": "[159:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_adr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "read_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "word_wen", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "byte_wen", "type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "rd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[159:0]" }, { "direction": "out", "name": "so_w", "type": "wire", "width": "" }, { "direction": "out", "name": "so_r", "type": "wire", "width": "" }, { "direction": "in", "name": "wen", "type": "wire", "width": "" }, { "direction": "in", "name": "ren", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rd_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" } ], "bw_r_tlb_data_ram": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlb_rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_auto", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "cache_ptag_w0", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w1", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w2", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w3", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_set_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlb_bypass_va", "type": "wire", "width": "[12:10]" }, { "direction": "in", "name": "tlb_bypass", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_soft_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "tlb_rd_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "tlb_pgnum", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_pgnum_crit", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_cam_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "cache_way_hit", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "cache_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_writeable", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "remains", "type": "wire", "width": "" }, { "direction": "in", "name": "if", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_tag", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_vld_tmp", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index", "type": "wire", "width": "[6-1:0]" }, { "direction": "in", "name": "tlb_index", "type": "wire", "width": "[6-1:0]" }, { "direction": "in", "name": "tlb_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_entry_vld", "type": "wire", "width": "[64-1:0]" }, { "direction": "in", "name": "wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "demap_other", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_data", "type": "wire", "width": "[53:0]" }, { "direction": "in", "name": "cam_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "cam_hit", "type": "wire", "width": "[64-1:0]" }, { "direction": "out", "name": "demap_hit", "type": "wire", "width": "[64-1:0]" }, { "direction": "out", "name": "tlb_entry_used", "type": "wire", "width": "[64-1:0]" }, { "direction": "out", "name": "tlb_entry_locked", "type": "wire", "width": "[64-1:0]" }, { "direction": "out", "name": "rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "mismatch", "type": "wire", "width": "[64-1:0]" }, { "direction": "in", "name": "rd_data", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_index", "type": "wire", "width": "[(6 - 1):0]" }, { "direction": "in", "name": "cam_hit_any", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "rd_tte_data", "type": "wire", "width": "[42:0]" } ], "bw_r_tlb_tag_ram": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": 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"width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dffr_async": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dffr_async_ns": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" 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"name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { 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"direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", 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"in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ], "ALU": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_o", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_o_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_o_2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "AR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PRE_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ROM_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_PRE_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_ROM_o", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "EP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LM_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CE_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ], "BREG": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_o", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_o_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_o_2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "AR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PRE_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ROM_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_PRE_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_ROM_o", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "EP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LM_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CE_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ], "IR": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_o", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_o_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_o_2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "AR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PRE_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ROM_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_PRE_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_ROM_o", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "EP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LM_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CE_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", 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"direction": "out", "name": "EI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": 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"direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": 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"direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ], "NANOCODE_ROM": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_o", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_o_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_o_2", "type": "wire", "width": "[3:0]" }, { "direction": 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"direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", 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"direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ], "SRAM": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_o", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_o_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_o_2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "AR_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "PRE_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "ROM_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_PRE_o", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "NANO_ROM_o", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "EP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CP_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LM_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CE_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EI_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CS_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EA_o", "type": "wire", "width": "" }, { "direction": "out", "name": "SU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "AD_o", "type": "wire", "width": "" }, { "direction": "out", "name": "EU_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LB_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "LOAD_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "CLEAR_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "INC_MICRO_o", "type": "wire", "width": "" }, { "direction": "out", "name": "B_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ALU_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "A_out", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "OR_out", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "EP", "type": "wire", "width": "" }, { "direction": "in", "name": "CP", "type": "wire", "width": "" }, { "direction": "out", "name": "PC_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "LM", "type": "wire", "width": "" }, { "direction": "in", "name": "PC_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "MAR_OUT", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "CE", "type": "wire", "width": "" }, { "direction": "in", "name": "MAR_IN", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "SRAM_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LI", "type": "wire", "width": "" }, { "direction": "in", "name": "EI", "type": "wire", "width": "" }, { "direction": "in", "name": "SRAM_IN", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "IR_OUT_1", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "IR_OUT_2", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "IR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "CS", "type": "wire", "width": "" }, { "direction": "out", "name": "AR_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "AR_ROM_IN", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "LOAD_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "INC_MICRO", "type": "wire", "width": "" }, { "direction": "in", "name": "CLEAR_MICRO", "type": "wire", "width": "" }, { "direction": "out", "name": "PRE_OUT", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "PRE_IN", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "ROM_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "MCR_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_PRE_OUT", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "NANO_PRE_IN", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "NANO_ROM_OUT", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "NANO_ROM_IN", "type": "wire", "width": "[16:0]" }, { "direction": "in", "name": "ACC_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LA", "type": "wire", "width": "" }, { "direction": "in", "name": "EA", "type": "wire", "width": "" }, { "direction": "out", "name": "ACC_ALU", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "ACC_BUS", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "B_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LB", "type": "wire", "width": "" }, { "direction": "out", "name": "B_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_A", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "ALU_B", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "SU", "type": "wire", "width": "" }, { "direction": "in", "name": "AD", "type": "wire", "width": "" }, { "direction": "in", "name": "EU", "type": "wire", "width": "" }, { "direction": "out", "name": "ALU_OUT", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "O_IN", "type": "wire", "width": "[8:0]" }, { "direction": "in", "name": "LO", "type": "wire", "width": "" }, { "direction": "out", "name": "O_OUT", "type": "wire", "width": "[8:0]" } ] }, "top_modules": [ "ACC", "ADDR_ROM", "ALU", "BREG", "IR", "M3CPU8", "MAR", "MICROCODE_ROM", "MICRO_PROG_COUNTER", "NANOCODE_DECODER", "NANOCODE_ROM", "NANO_PROG_COUNTER", "OREG", "PC", "SRAM" ] }, { "namespace": "opencores", "name": "sd_card_controller", "latest": "master", "versions": [ "master" ], "description": "SD card host controller with Wishbone host bus, supporting standard SD/SDHC commands and SPI-mode interfacing.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/sd_card_controller.git", "tags": [ "access", "altera", "bistable", "buffer", "controller", "cyclic", "datapath", "detect", "divider", "monostable", "redundancy", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T23:36:17Z", "updated_at": "2013-09-10T16:51:33+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "top_ports": { "generic_dpram": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rrst", "type": "wire", "width": "" }, { "direction": "in", "name": "rce", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrst", "type": "wire", "width": "" }, { "direction": "in", "name": "wce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "waddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "register", "type": "wire", "width": "" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "start", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "finish", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "wraddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "rdaddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclock", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclocken", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclock", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclocken", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "CLKA", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTA", "type": "wire", "width": "" }, { "direction": "in", "name": "ENA", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRA", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "CLKB", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTB", "type": "wire", "width": "" }, { "direction": "in", "name": "ENB", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRB", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIB", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEB", "type": "wire", "width": "" }, { "direction": "out", "name": "DOB", "type": "wire", "width": "[dwidth-1:0]" } ], "sdc_controller": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "card_detect", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "m_wb_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_wb_we_o", "type": "wire", "width": "" }, { "direction": "in", "name": "m_wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "m_wb_stb_o", "type": "wire", "width": "" }, { "direction": "in", "name": "m_wb_ack_i", "type": "wire", "width": "" }, { "direction": "out", "name": "m_wb_cti_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_wb_bte_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk_i_pad", "type": "wire", "width": "" }, { "direction": "out", "name": "int_cmd", "type": "wire", "width": "" } ], "xilinx_ram_dp": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rrst", "type": "wire", "width": "" }, { "direction": "in", "name": "rce", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrst", "type": "wire", "width": "" }, { "direction": "in", "name": "wce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "waddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "register", "type": "wire", "width": "" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "start", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "finish", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "wraddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "rdaddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclock", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclocken", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclock", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclocken", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "CLKA", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTA", "type": "wire", "width": "" }, { "direction": "in", "name": "ENA", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRA", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "CLKB", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTB", "type": "wire", "width": "" }, { "direction": "in", "name": "ENB", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRB", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIB", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEB", "type": "wire", "width": "" }, { "direction": "out", "name": "DOB", "type": "wire", "width": "[dwidth-1:0]" } ] }, "top_modules": [ "generic_dpram", "sdc_controller", "xilinx_ram_dp" ] }, { "namespace": "opencores", "name": "sdcard_mass_storage_controller", "latest": "master", "versions": [ "master" ], "description": "SD card mass-storage controller with FAT16/FAT32 file system support, designed for embedded applications requiring persistent storage.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/sdcard_mass_storage_controller.git", "tags": [ "asynchronous", "comparator", "controller", "counter", "divider", "physical", "receiver", "redundancy", "transmit", "transmitter", "versatile", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T23:36:17Z", "updated_at": "2010-10-15T13:30:30+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "top_ports": { "CRC_7": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sd_cmd_phy": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sd_controller_fifo_wba": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sd_counter": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sd_data_phy": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sd_fifo": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "DAT_dat_o", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "DAT_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "start_dat", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "fifo_acces", "type": "wire", "width": "" } ], "sdc_controller": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "m_wb_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "m_wb_we_o", "type": "wire", "width": "" }, { "direction": "in", "name": "m_wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m_wb_cyc_o", "type": "wire", "width": "" }, { "direction": "out", "name": "m_wb_stb_o", "type": "wire", "width": "" }, { "direction": "in", "name": "m_wb_ack_i", "type": "wire", "width": "" }, { "direction": "out", "name": "m_wb_cti_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "m_wb_bte_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk_i_pad", "type": "wire", "width": "" }, { "direction": "out", "name": "int_a", "type": "wire", "width": "" } ], "versatile_fifo_async_cmp": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_dat_dat_i", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_out_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "sd_dat_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_out_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_clk_o_pad", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "cmd_dat_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_dat_o", "type": "wire", "width": "" }, { "direction": "out", "name": "cmd_oe_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_adr_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "sd_re_o", "type": "wire", "width": "" }, { "direction": "in", "name": "fifo_full", "type": "wire", "width": "[1:2]" }, { "direction": "in", "name": "fifo_empty", "type": "wire", "width": "[1:2]" }, { "direction": "out", "name": "start_dat_t", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "fifo_acces_token", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[9:1]" }, { "direction": "out", "name": "q_bin", "type": "wire", "width": "[9:1]" }, { "direction": "in", "name": "cke", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wptr", "type": "wire", "width": "[N:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "BITVAL", "type": "wire", "width": "" }, { "direction": "in", "name": "Enable", "type": "wire", "width": "" }, { "direction": "in", "name": "CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "RST", "type": "wire", "width": "" }, { "direction": "out", "name": "CRC", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "DAT_oe_o", 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"wire", "width": "" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wb_sel_i", "type": "wire", "width": "[dw/8-1:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wb_cyc_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_cti_i", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "sdr_cke", "type": "wire", "width": "" }, { "direction": "out", "name": "sdr_cs_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sdr_ras_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sdr_cas_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sdr_we_n", "type": "wire", "width": "" }, { "direction": "out", "name": "sdr_dqm", "type": "wire", "width": "[SDR_BW-1:0]" }, { "direction": "out", "name": "sdr_ba", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "sdr_addr", "type": "wire", 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"wire", "width": "[6:0]" }, { "direction": "in", "name": "index1_x", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "index_sel_x", "type": "wire", "width": "" }, { "direction": "in", "name": "dec_wrway_x", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rdreq_x", "type": "wire", "width": "" }, { "direction": "in", "name": "wrreq_x", "type": "wire", "width": "" }, { "direction": "in", "name": "wrtag_w0_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w1_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w2_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wrtag_w3_y", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "rdtag_w0_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w1_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w2_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "rdtag_w3_y", "type": "wire", "width": "[32:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "dec_wrway_y", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "way", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "flops", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "out", "name": "has", "type": "wire", "width": "" }, { "direction": "out", "name": "behavior", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" } ], "bw_r_irf_72_4x1_mux": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "save", "type": "wire", "width": "" }, { "direction": "in", "name": "save_addr", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "restore", "type": "wire", "width": "" }, { "direction": "in", "name": "restore_addr", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wrens", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_data0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data3", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "rd_thread", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sel", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "x0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x3", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "y", "type": "wire", "width": "[71:0]" } ], "bw_r_irf_core": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_tid_s2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_exu_rs1_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_rs2_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_rs3_s", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_exu_ren1_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren2_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren3_s", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_wen_w", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_wen_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "ecl_irf_rd_m", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ecl_irf_rd_g", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "byp_irf_rd_data_w", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "byp_irf_rd_data_w2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "ecl_irf_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ecl_irf_tid_g", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_old_lo_cwp_e", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "rml_irf_new_lo_cwp_e", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "rml_irf_old_e_cwp_e", "type": "wire", "width": "[2:1]" }, { "direction": "in", "name": "rml_irf_new_e_cwp_e", "type": "wire", "width": "[2:1]" }, { "direction": "in", "name": "rml_irf_swap_even_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_swap_odd_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_swap_local_e", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_kill_restore_w", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_cwpswap_tid_e", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_old_agp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_new_agp", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "rml_irf_swap_global", "type": "wire", "width": "" }, { "direction": "in", "name": "rml_irf_global_tid", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "irf_byp_rs1_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs2_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3_data_d_l", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3h_data_d_l", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren1_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren2_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_exu_ren3_d", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_rs1", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs2", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs3", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rs3h", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "irf_byp_rs1_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs2_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "irf_byp_rs3h_data_d", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en2", "type": "wire", "width": "" }, { "direction": "in", "name": "active_win_thr_rd_w_neg", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "active_win_thr_rd_w2_neg", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "thr_rd_w_neg", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "thr_rd_w2_neg", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "swap_global_d1_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_global_d2", "type": "wire", "width": "" }, { "direction": "in", "name": "global_tid_d1", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "global_tid_d2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "old_agp_d1", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "new_agp_d2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "swap_local_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_local_w", "type": "wire", "width": "" }, { "direction": "in", "name": "old_lo_cwp_m", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "new_lo_cwp_w", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "swap_even_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_even_w", "type": "wire", "width": "" }, { "direction": "in", "name": "old_e_cwp_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "new_e_cwp_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "swap_odd_m_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "swap_odd_w", "type": "wire", "width": "" }, { "direction": "in", "name": "cwpswap_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cwpswap_tid_w", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "kill_restore_w", "type": "wire", "width": "" }, { "direction": "out", "name": "disabled", "type": "wire", "width": "" } ], "bw_r_irf_register": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "save", "type": "wire", "width": "" }, { "direction": "in", "name": "save_addr", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "restore", "type": "wire", "width": "" }, { "direction": "in", "name": "restore_addr", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wrens", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_data0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "wr_data3", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "rd_thread", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sel", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "x0", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x1", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "[71:0]" }, { "direction": "in", "name": "x3", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "y", "type": "wire", "width": "[71:0]" } ], "bw_r_l2d": [ { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "col_offset", "type": "wire", "width": "" }, { "direction": "in", "name": "decc_in", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "decc_read_in", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "efc_scdata_fuse_clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "efc_scdata_fuse_clk2", "type": "wire", "width": "" }, { "direction": "in", "name": "fuse_l2d_data_in", "type": "wire", "width": "" }, { "direction": "in", "name": "fuse_l2d_rden", "type": "wire", "width": "" }, { "direction": "in", "name": "fuse_l2d_rid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "fuse_l2d_wren", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "fuse_read_data_in", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_write_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "scbuf_scdata_fbdecc_bot", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "scbuf_scdata_fbdecc_top", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "scdata_scbuf_decc_bot", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "scdata_scbuf_decc_top", "type": "wire", "width": "[155:0]" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "set", "type": "wire", "width": "[9:0]" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "way_sel", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "word_en", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "out", "name": "fuse_l2d_rid_buf", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "fuse_l2d_data_in_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "arst_l_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "se_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "sehold_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "fuse_l2d_rden_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "fuse_l2d_wren_buf", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "fuse_clk1_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "fuse_clk2_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_write_disable_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "col_offset_buf", "type": "wire", "width": "" }, { "direction": "out", "name": "decc_in_buf", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "decc_out", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "l2d_fuse_data_out", "type": "wire", "width": "" }, { "direction": "out", "name": "scbuf_scdata_fbdecc_bot_buf", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "scbuf_scdata_fbdecc_top_buf", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "scdata_scbuf_decc_bot_buf", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "scdata_scbuf_decc_top_buf", "type": "wire", "width": "[155:0]" }, { "direction": "out", "name": "set_buf", "type": "wire", "width": "[9:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "way_sel_buf", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "word_en_buf", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "wr_en_buf", "type": "wire", "width": "" } ], "bw_r_l2t": [ { "direction": "in", "name": "index", "type": "wire", "width": "[9:0]" }, { "direction": "in", "name": "bist_index", "type": "wire", "width": "[9:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_rd_en", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_way", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "bist_wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_wrdata0", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wrdata1", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "bist_wrdata1", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "lkup_tag_d1", "type": "wire", "width": "[27:1]" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "tag_stm", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "fuse_l2t_wren", "type": "wire", "width": "" }, { "direction": "in", "name": "fuse_l2t_rid", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "fuse_l2t_repair_value", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "fuse_l2t_repair_en", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "efc_sctag_fuse_clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "l2t_fuse_repair_value", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "l2t_fuse_repair_en", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "way_sel", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "way_sel_1", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "tag_way0", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way1", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way2", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way3", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way4", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way5", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way6", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way7", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way8", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way9", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way10", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way11", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_en", "type": "wire", "width": "" }, { "direction": "in", "name": "way", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "wd_b_l", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "lkuptag", "type": "wire", "width": "[27:1]" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sin", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_rid", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "gbl_red_reg_en", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "gbl_red_reg_d", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "fclk1", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_bank_id_top", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_bank_id_bottom", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_wr_en", "type": "wire", "width": "" }, { "direction": "out", "name": "sout", "type": "wire", "width": "" }, { "direction": "out", "name": "wayselect0", "type": "wire", "width": "" }, { "direction": "out", "name": "wayselect1", "type": "wire", "width": "" }, { "direction": "out", "name": "red_reg_q_array2", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "red_reg_enq_array2", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "does", "type": "wire", "width": "" }, { "direction": "out", "name": "signals", "type": "wire", "width": "" }, { "direction": "out", "name": "will", "type": "wire", "width": "" } ], "bw_r_l2t_subbank": [ { "direction": "in", "name": "index", "type": "wire", "width": "[9:0]" }, { "direction": "in", "name": "bist_index", "type": "wire", "width": "[9:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_rd_en", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_way", "type": "wire", "width": "[11:0]" }, { "direction": "in", "name": "bist_wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_wrdata0", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wrdata1", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "bist_wrdata1", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "lkup_tag_d1", "type": "wire", "width": "[27:1]" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "tag_stm", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "fuse_l2t_wren", "type": "wire", "width": "" }, { "direction": "in", "name": "fuse_l2t_rid", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "fuse_l2t_repair_value", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "fuse_l2t_repair_en", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "efc_sctag_fuse_clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "l2t_fuse_repair_value", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "l2t_fuse_repair_en", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "way_sel", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "way_sel_1", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "tag_way0", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way1", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way2", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way3", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way4", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way5", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way6", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way7", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way8", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way9", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way10", "type": "wire", "width": "[27:0]" }, { "direction": "out", "name": "tag_way11", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_en", "type": "wire", "width": "" }, { "direction": "in", "name": "way", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "wd_b_l", "type": "wire", "width": "[27:0]" }, { "direction": "in", "name": "lkuptag", "type": "wire", "width": "[27:1]" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sin", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_rid", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "gbl_red_reg_en", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "gbl_red_reg_d", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "fclk1", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_bank_id_top", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_bank_id_bottom", "type": "wire", "width": "" }, { "direction": "in", "name": "gbl_red_wr_en", "type": "wire", "width": "" }, { "direction": "out", "name": "sout", "type": "wire", "width": "" }, { "direction": "out", "name": "wayselect0", "type": "wire", "width": "" }, { "direction": "out", "name": "wayselect1", "type": "wire", "width": "" }, { "direction": "out", "name": "red_reg_q_array2", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "red_reg_enq_array2", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "does", "type": "wire", "width": "" }, { "direction": "out", "name": "signals", "type": "wire", "width": "" }, { "direction": "out", "name": "will", "type": "wire", "width": "" } ], "bw_r_rf16x128d": [ { "direction": "in", "name": "din", "type": "wire", "width": "[127:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_wl", "type": "wire", "width": "[15:0]" }, { "direction": "in", "name": "read_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[127:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "when", "type": "wire", "width": "" } ], "bw_r_rf16x2": [ { "direction": "in", "name": "din", "type": "wire", "width": "[159:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_adr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "read_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "word_wen", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "byte_wen", "type": "wire", "width": "[19:0]" }, { "direction": "in", "name": "rd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[159:0]" }, { "direction": "out", "name": "so_w", "type": "wire", "width": "" }, { "direction": "out", "name": "so_r", "type": "wire", "width": "" }, { "direction": "in", "name": "when", "type": "wire", "width": "" }, { "direction": "in", "name": "wen", "type": "wire", "width": "" }, { "direction": "in", "name": "ren", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rd_addr", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" } ], "bw_r_rf32x108": [ { "direction": "in", "name": "din", "type": "wire", "width": "[107:0]" }, { "direction": "in", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_adr2", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "sel_rdaddr1", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_adr", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "read_en", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_en", "type": "wire", "width": "" }, { "direction": "in", "name": "word_wen", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "reset_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[107:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "when", "type": "wire", "width": "" } ], "bw_r_tlb_data_ram": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlb_rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_auto", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "cache_ptag_w0", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w1", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w2", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w3", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_set_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlb_bypass_va", "type": "wire", "width": "[12:10]" }, { "direction": "in", "name": "tlb_bypass", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_soft_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "tlb_rd_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "tlb_pgnum", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_pgnum_crit", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_cam_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "cache_way_hit", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "cache_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_writeable", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "remains", "type": "wire", "width": "" }, { "direction": "in", "name": "if", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_tag", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_vld_tmp", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_entry_vld", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "demap_other", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_data", "type": "wire", "width": "[53:0]" }, { "direction": "in", "name": "cam_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "cam_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "demap_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_used", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_locked", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "mismatch", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "rd_data", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_index", "type": "wire", "width": "[(6 - 1):0]" }, { "direction": "in", "name": "cam_hit_any", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "rd_tte_data", "type": "wire", "width": "[42:0]" } ], "bw_r_tlb_data_ram_fpga": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlb_rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_auto", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "cache_ptag_w0", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w1", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w2", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w3", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_set_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlb_bypass_va", "type": "wire", "width": "[12:10]" }, { "direction": "in", "name": "tlb_bypass", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_soft_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "tlb_rd_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "tlb_pgnum", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_pgnum_crit", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_cam_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "cache_way_hit", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "cache_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_writeable", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "remains", "type": "wire", "width": "" }, { "direction": "in", "name": "if", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_tag", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_vld_tmp", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_entry_vld", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "demap_other", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_data", "type": "wire", "width": "[53:0]" }, { "direction": "in", "name": "cam_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "cam_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "demap_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_used", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_locked", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "mismatch", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "rd_data", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_index", "type": "wire", "width": "[(6 - 1):0]" }, { "direction": "in", "name": "cam_hit_any", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "rd_tte_data", "type": "wire", "width": "[42:0]" } ], "bw_r_tlb_tag_ram": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlb_rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_auto", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "cache_ptag_w0", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w1", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w2", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w3", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_set_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlb_bypass_va", "type": "wire", "width": "[12:10]" }, { "direction": "in", "name": "tlb_bypass", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_soft_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "tlb_rd_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "tlb_pgnum", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_pgnum_crit", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_cam_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "cache_way_hit", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "cache_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_writeable", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "remains", "type": "wire", "width": "" }, { "direction": "in", "name": "if", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_tag", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_vld_tmp", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_entry_vld", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "demap_other", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_data", "type": "wire", "width": "[53:0]" }, { "direction": "in", "name": "cam_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "cam_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "demap_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_used", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_locked", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "mismatch", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "rd_data", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_index", "type": "wire", "width": "[(6 - 1):0]" }, { "direction": "in", "name": "cam_hit_any", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "rd_tte_data", "type": "wire", "width": "[42:0]" } ], "bw_r_tlb_tag_ram_fpga": [ { "direction": "in", "name": "tlb_cam_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_cam_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "tlb_demap_key", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlb_addr_mask_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_ctxt", "type": "wire", "width": "[12:0]" }, { "direction": "in", "name": "tlb_wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlb_rd_tag_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_rw_index", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlb_rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_auto", "type": "wire", "width": "" }, { "direction": "in", "name": "tlb_demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "cache_ptag_w0", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w1", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w2", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_ptag_w3", "type": "wire", "width": "[29:0]" }, { "direction": "in", "name": "cache_set_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlb_bypass_va", "type": "wire", "width": "[12:10]" }, { "direction": "in", "name": "tlb_bypass", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "adj", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_soft_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "tlb_rd_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "tlb_pgnum", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_pgnum_crit", "type": "wire", "width": "[39:10]" }, { "direction": "out", "name": "tlb_cam_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "cache_way_hit", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "cache_hit", "type": "wire", "width": "" }, { "direction": "out", "name": "tlb_writeable", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" }, { "direction": "in", "name": "remains", "type": "wire", "width": "" }, { "direction": "in", "name": "if", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_tag", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_vld_tmp", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index", "type": "wire", "width": "[`TLB_INDEX_WIDTH-1:0]" }, { "direction": "in", "name": "tlb_index_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rw_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlb_entry_vld", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "wr_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_pid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "demap_all", "type": "wire", "width": "" }, { "direction": "in", "name": "demap_other", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_data", "type": "wire", "width": "[53:0]" }, { "direction": "in", "name": "cam_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "cam_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "demap_hit", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_used", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "tlb_entry_locked", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "out", "name": "rd_tte_tag", "type": "wire", "width": "[58:0]" }, { "direction": "out", "name": "mismatch", "type": "wire", "width": "[`TLB_ENTRIES-1:0]" }, { "direction": "in", "name": "rd_data", "type": "wire", "width": "" }, { "direction": "in", "name": "cam_index", "type": "wire", "width": "[(6 - 1):0]" }, { "direction": "in", "name": "cam_hit_any", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_tte_data", "type": "wire", "width": "[42:0]" }, { "direction": "out", "name": "rd_tte_data", "type": "wire", "width": "[42:0]" } ], "bw_rf_16x65": [ { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "csn_rd", "type": "wire", "width": "" }, { "direction": "in", "name": "csn_wr", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "testmux_sel", "type": "wire", "width": "" }, { "direction": "in", "name": "scan_en", "type": "wire", "width": "" }, { "direction": "in", "name": "margin", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "rd_a", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_a", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[64:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "do", "type": "wire", "width": "[64:0]" }, { "direction": "out", "name": "listen_out", "type": "wire", "width": "[64:0]" } ], "bw_rf_16x81": [ { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "wr_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "csn_rd", "type": "wire", "width": "" }, { "direction": "in", "name": "csn_wr", "type": "wire", "width": "" }, { "direction": "in", "name": "hold", "type": "wire", "width": "" }, { "direction": "in", "name": "testmux_sel", "type": "wire", "width": "" }, { "direction": "in", "name": "scan_en", "type": "wire", "width": "" }, { "direction": "in", "name": "margin", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "rd_a", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "wr_a", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[80:0]" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "do", "type": "wire", "width": "[80:0]" }, { "direction": "out", "name": "listen_out", "type": "wire", "width": "[80:0]" } ], "cluster_header_ctu": [ { "direction": "in", "name": "gclk", "type": "wire", "width": "" }, { "direction": "in", "name": "cluster_cken", "type": "wire", "width": "" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "grst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "adbginit_l", "type": "wire", "width": "" }, { "direction": "in", "name": "gdbginit_l", "type": "wire", "width": "" }, { "direction": "out", "name": "dbginit_l", "type": "wire", "width": "" }, { "direction": "out", "name": "cluster_grst_l", "type": "wire", "width": "" }, { "direction": "out", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" } ], "cluster_header_dup": [ { "direction": "in", "name": "gclk", "type": "wire", "width": "" }, { "direction": "in", "name": "cluster_cken", "type": "wire", "width": "" }, { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "grst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "adbginit_l", "type": "wire", "width": "" }, { "direction": "in", "name": "gdbginit_l", "type": "wire", "width": "" }, { "direction": "out", "name": "dbginit_l", "type": "wire", "width": "" }, { "direction": "out", "name": "cluster_grst_l", "type": "wire", "width": "" }, { "direction": "out", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" } ], "cluster_header_sync": [ { "direction": "out", "name": "dram_rx_sync_local", "type": "wire", "width": "" }, { "direction": "out", "name": "dram_tx_sync_local", "type": "wire", "width": "" }, { "direction": "out", "name": "jbus_rx_sync_local", "type": "wire", "width": "" }, { "direction": "out", "name": "jbus_tx_sync_local", "type": "wire", "width": "" }, { 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"rst_warm", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_hit", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "rw_addr", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "inv_mask", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lkup_hit", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[31:0]" } ], "dcm_panel_pair": [ { "direction": "out", "name": "row_hit", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data0", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data1", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data2", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data3", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "cam_en", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "inv_mask0", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "inv_mask1", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "inv_mask2", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "inv_mask3", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "si_0", "type": "wire", "width": "" }, { "direction": "out", "name": "so_0", "type": "wire", "width": "" }, { "direction": "in", "name": "si_1", "type": "wire", "width": "" }, { "direction": "out", "name": "so_1", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold_0", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold_1", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, 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"name": "wr_data1", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wr_data2", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "wr_data3", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_tri_en", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_warm", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_hit", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wr_data", "type": "wire", "width": "[32:0]" }, { "direction": "in", "name": "rw_addr", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "inv_mask", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lkup_hit", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "rd_data", "type": "wire", "width": "[31:0]" } ], "dff_ns": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dff_s": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dff_sscan": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dffe_ns": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "dffe_s": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { 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"direction": "in", "name": "sel7_l", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" } ], "dp_mux8ds": [ { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sel2_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sel3_l", "type": "wire", "width": "" }, { "direction": "in", "name": "in4", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel4_l", "type": "wire", "width": "" }, { "direction": "in", "name": "in5", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in6", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in7", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel5_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sel6_l", "type": "wire", "width": "" }, { "direction": "in", "name": "sel7_l", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" } ], "eth_cop": [ { "direction": "in", "name": "wb_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "m1_wb_adr_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "m1_wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "m1_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "out", "name": "m1_wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m1_wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "m2_wb_adr_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "m2_wb_sel_i", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "m2_wb_cyc_i", "type": "wire", "width": "" }, { "direction": "out", "name": "m2_wb_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "m2_wb_ack_o", "type": "wire", "width": "" }, { "direction": "in", "name": "s1_wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s1_wb_ack_i", "type": "wire", "width": "" }, { "direction": "out", "name": "s1_wb_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "s1_wb_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "s1_wb_we_o", "type": "wire", "width": "" }, { "direction": "in", "name": "s2_wb_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "s2_wb_ack_i", "type": "wire", "width": "" }, { "direction": "out", "name": "s2_wb_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "s2_wb_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "s2_wb_we_o", "type": "wire", "width": "" } ], "fpu_bufrpt_grp64": [ { "direction": "in", "name": "in", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[63:0]" } ], "fpu_rptr_fp_cpx_grp16": [ { "direction": "in", "name": "in", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[3:0]" } ], "fpu_rptr_inq": [ { "direction": "in", "name": "in", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[3:0]" } ], "fpu_rptr_pcx_fpio_grp16": [ { "direction": "in", "name": "in", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[3:0]" } ], "lsu": [ { "direction": "in", "name": "arst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "bist_ctl_reg_out", "type": "wire", "width": "[10:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "const_cpuid", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ctu_sscan_tid", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "efc_spc_dfuse_ashift", "type": "wire", "width": "" }, { "direction": "in", "name": "efc_spc_dfuse_data", "type": "wire", "width": "" }, { "direction": "in", "name": "efc_spc_dfuse_dshift", "type": "wire", "width": "" }, { "direction": "in", "name": "efc_spc_fuse_clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "efc_spc_fuse_clk2", "type": "wire", "width": "" }, { "direction": "in", "name": "exu_lsu_rs2_data_e", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "exu_lsu_rs3_data_e", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "exu_tlu_misalign_addr_jmpl_rtn_m", "type": "wire", "width": "" }, { "direction": "in", "name": "exu_tlu_va_oor_m", "type": "wire", "width": "" }, { "direction": "in", "name": "ffu_lsu_blk_st_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ffu_lsu_blk_st_va_e", "type": "wire", "width": "[5:3]" }, { "direction": "in", "name": "ffu_lsu_fpop_rq_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "ffu_lsu_kill_fst_w", "type": "wire", "width": "" }, { "direction": "in", "name": "gdbginit_l", "type": "wire", "width": "" }, { "direction": "in", "name": "grst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_alt_space_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_alt_space_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_asi_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_asi_rd_unc", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_casa_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_destid_s", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "ifu_lsu_fwd_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_fwd_wr_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ibuf_busy", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_imm_asi_d", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "ifu_lsu_imm_asi_vld_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_inv_clear", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ld_inst_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldst_dbl_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldst_fp_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldst_size_e", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_lsu_ldstub_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldxa_data_vld_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldxa_data_w2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "ifu_lsu_ldxa_illgl_va_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_ldxa_tid_w2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_lsu_memref_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_nceen", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "ifu_lsu_pcxpkt_e", "type": "wire", "width": "[51:0]" }, { "direction": "in", "name": "ifu_lsu_pcxreq_d", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_pref_inst_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_rd_e", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "ifu_lsu_sign_ext_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_st_inst_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_swap_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_lsu_thrid_s", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_tlu_flsh_inst_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_tlu_flush_m", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_tlu_inst_vld_m", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_tlu_mb_inst_e", "type": "wire", "width": "" }, { "direction": "in", "name": "ifu_tlu_sraddr_d", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "ifu_tlu_thrid_e", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "ifu_tlu_wsr_inst_d", "type": "wire", "width": "" }, { "direction": "in", "name": "mbist_dcache_index", "type": "wire", "width": "[6:0]" }, { "direction": "in", "name": "mbist_dcache_read", "type": "wire", "width": "" }, { "direction": "in", "name": "mbist_dcache_way", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "mbist_dcache_word", "type": "wire", "width": "" }, { "direction": "in", "name": "mbist_dcache_write", "type": "wire", "width": "" }, { "direction": "in", "name": "mbist_write_data", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "mem_write_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "mux_drive_disable", "type": "wire", "width": "" }, { "direction": "in", "name": "pcx_spc_grant_px", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "sehold", "type": "wire", "width": "" }, { "direction": "in", "name": "spu_lsu_int_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "spu_lsu_ldxa_data_vld_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "spu_lsu_ldxa_data_w2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "spu_lsu_ldxa_illgl_va_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "spu_lsu_ldxa_tid_w2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "spu_lsu_stxa_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "spu_lsu_stxa_ack_tid", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "spu_lsu_unc_error_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_l", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dsfsr_flt_vld", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_dtlb_data_rd_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_actxt_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_all_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_nctxt_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_pctxt_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_sctxt_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_dmp_vld_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_invalidate_all_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_rw_index_g", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "tlu_dtlb_rw_index_vld_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_tag_rd_g", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_dtlb_tte_data_w2", "type": "wire", "width": "[42:0]" }, { "direction": "in", "name": "tlu_dtlb_tte_tag_w2", "type": "wire", "width": "[58:0]" }, { "direction": "in", "name": "tlu_early_flush_pipe2_w", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_early_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_exu_early_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_idtlb_dmp_key_g", "type": "wire", "width": "[40:0]" }, { "direction": "in", "name": "tlu_idtlb_dmp_thrid_g", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "tlu_lsu_asi_m", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "tlu_lsu_asi_update_m", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_hpstate_en", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_hpv_priv", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_int_ld_ill_va_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_int_ldxa_data_w2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "tlu_lsu_int_ldxa_vld_w2", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_ldxa_async_data_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_ldxa_tid_w2", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "tlu_lsu_pcxpkt", "type": "wire", "width": "[25:0]" }, { "direction": "in", "name": "tlu_lsu_priv_trap_m", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_pstate_am", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_pstate_cle", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_pstate_priv", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_redmode", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_redmode_rst_d1", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "tlu_lsu_stxa_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "tlu_lsu_stxa_ack_tid", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "tlu_lsu_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "tlu_lsu_tl_zero", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "bist_ctl_reg_in", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "bist_ctl_reg_wr_en", "type": "wire", "width": "" }, { "direction": "out", "name": "ifu_tlu_flush_fd2_w", "type": "wire", "width": "" }, { "direction": "out", "name": "ifu_tlu_flush_fd3_w", "type": "wire", "width": "" }, { "direction": "out", "name": "ifu_tlu_flush_fd_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_asi_reg0", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_asi_reg1", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_asi_reg2", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_asi_reg3", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_dmmu_sfsr_trp_wr", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_dsfsr_din_g", "type": "wire", "width": "[23:0]" }, { "direction": "out", "name": "lsu_exu_dfill_data_w2", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "lsu_exu_dfill_vld_w2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_exu_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_exu_ldst_miss_w2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_exu_rd_m", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "lsu_exu_st_dtlb_perr_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_exu_thr_m", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_ffu_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_blk_asi_e", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_ld_data", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "lsu_ffu_ld_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_st_dtlb_perr_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_stb_full0", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_stb_full1", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_stb_full2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_stb_full3", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ictag_mrgn", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_asi_addr", "type": "wire", "width": "[17:0]" }, { "direction": "out", "name": "lsu_ifu_asi_load", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_asi_state", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_ifu_asi_thrid", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_ifu_asi_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_cpxpkt_i1", "type": "wire", "width": "[`CPX_VLD-1:0]" }, { "direction": "out", "name": "lsu_ifu_cpxpkt_vld_i1", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_dc_parity_error_w2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_dcache_data_perror", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_dcache_tag_perror", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_direct_map_l1", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_error_tid", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_ifu_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_icache_en", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_io_error", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_itlb_en", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_l2_corr_error", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_l2_unc_error", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_ld_icache_index", "type": "wire", "width": "[11:5]" }, { "direction": "out", "name": "lsu_ifu_ld_pcxpkt_tid", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_ifu_ld_pcxpkt_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_ldst_cmplt", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_ldst_miss_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_ldsta_internal_e", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_pcxpkt_ack_d", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_stallreq", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_stbcnt0", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_stbcnt1", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_stbcnt2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_stbcnt3", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_ifu_stxa_data", "type": "wire", "width": "[47:0]" }, { "direction": "out", "name": "lsu_ifu_tlb_data_su", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_tlb_data_ue", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ifu_tlb_tag_ue", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_itlb_mrgn", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_mamem_mrgn", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_mmu_defr_trp_taken_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_mmu_flush_pipe_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_mmu_rs3_data_g", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "lsu_pid_state0", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "lsu_pid_state1", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "lsu_pid_state2", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "lsu_pid_state3", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "lsu_spu_asi_state_e", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_spu_early_flush_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_spu_ldst_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_spu_stb_empty", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_spu_strm_ack_cmplt", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_t0_pctxt_state", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_t1_pctxt_state", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_t2_pctxt_state", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_t3_pctxt_state", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_tlu_async_tid_w2", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_tlu_async_ttype_vld_w2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_async_ttype_w2", "type": "wire", "width": "[6:0]" }, { "direction": "out", "name": "lsu_tlu_cpx_req", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_tlu_cpx_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_daccess_excptn_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_dcache_miss_w2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_tlu_defr_trp_taken_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_dmmu_miss_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_dside_ctxt_m", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_tlu_dtlb_done", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_early_flush2_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_early_flush_w", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_intpkt", "type": "wire", "width": "[17:0]" }, { "direction": "out", "name": "lsu_tlu_l2_dmiss", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_tlu_ldst_va_m", "type": "wire", "width": "[9:0]" }, { "direction": "out", "name": "lsu_tlu_misalign_addr_ldst_atm_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_pctxt_m", "type": "wire", "width": "[12:0]" }, { "direction": "out", "name": "lsu_tlu_pcxpkt_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_rs3_data_g", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "lsu_tlu_rsr_data_e", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_tlu_stb_full_w2", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "lsu_tlu_thrid_d", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_tlu_tlb_access_tid_m", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "lsu_tlu_tlb_asi_state_m", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_tlu_tlb_dmp_va_m", "type": "wire", "width": "[47:13]" }, { "direction": "out", "name": "lsu_tlu_tlb_ld_inst_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_tlb_ldst_va_m", "type": "wire", "width": "[10:0]" }, { "direction": "out", "name": "lsu_tlu_tlb_st_inst_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_ttype_m2", "type": "wire", "width": "[8:0]" }, { "direction": "out", "name": "lsu_tlu_ttype_vld_m2", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_wsr_inst_e", "type": "wire", "width": "" }, { "direction": "out", "name": "mbist_dcache_data_in", "type": "wire", "width": "[71:0]" }, { "direction": "out", "name": "spc_efc_dfuse_data", "type": "wire", "width": "" }, { "direction": "out", "name": "spc_pcx_atom_pq", "type": "wire", "width": "" }, { "direction": "out", "name": "spc_pcx_data_pa", "type": "wire", "width": "[`PCX_WIDTH-1:0]" }, { "direction": "out", "name": "spc_pcx_req_pq", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "cpx_spc_data_cx", "type": "wire", "width": "[`CPX_WIDTH-1:0]" }, { "direction": "in", "name": "spu_lsu_ldst_pckt", "type": "wire", "width": "[`PCX_WIDTH-1:0]" }, { "direction": "in", "name": "exu_lsu_ldst_va_e", "type": "wire", "width": "[47:0]" }, { "direction": "in", "name": "exu_lsu_early_va_e", "type": "wire", "width": "[10:3]" }, { "direction": "in", "name": "ffu_lsu_data", "type": "wire", "width": "[80:0]" }, { "direction": "out", "name": "lsu_asi_state", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_ifu_err_addr", "type": "wire", "width": "[47:4]" }, { "direction": "out", "name": "lsu_sscan_data", "type": "wire", "width": "[15:0]" }, { "direction": "out", "name": "ifu_tlu_inst_vld_m_bf1", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_ffu_bld_cnt_w", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "si0", "type": "wire", "width": "" }, { "direction": "out", "name": "so0", "type": "wire", "width": "" }, { "direction": "in", "name": "exu_tlu_wsr_data_m", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "lsu_tlu_nucleus_ctxt_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_tte_pg_sz_g", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "lsu_tlu_nonalt_ldst_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_squash_va_oor_m", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_wtchpt_trp_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_priv_violtn_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_daccess_prot_g", "type": "wire", "width": "" }, { "direction": "out", "name": "lsu_tlu_priv_action_g", "type": "wire", "width": "" } ], "mul_array1": [ { "direction": "in", "name": "rs1_l", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "rs2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "valid", "type": "wire", "width": "" }, { "direction": "in", "name": "areg", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "accreg", "type": "wire", "width": "[135:129]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_step", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[135:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "mux", "type": "wire", "width": "" }, { "direction": "in", "name": "bot", "type": "wire", "width": "" }, { "direction": "out", "name": "cout", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "sum", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "b6", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b3", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b8", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b2", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b1", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b7", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "b0", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b4", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b5", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "pcoutx2", "type": "wire", "width": "" }, { "direction": "out", "name": "psum", "type": "wire", "width": "[98:0]" }, { "direction": "out", "name": "pcout", "type": "wire", "width": "[98:0]" }, { "direction": "in", "name": "a1c", "type": "wire", "width": "[81:4]" }, { "direction": "in", "name": "pc", "type": "wire", "width": "[98:30]" }, { "direction": "in", "name": "ps", "type": "wire", "width": "[98:31]" }, { "direction": "in", "name": "a0s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a1s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a0c", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "n0", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "p0_l", "type": "wire", "width": "" }, { "direction": "in", "name": "am1", "type": "wire", "width": "" }, { "direction": "in", "name": "am2", "type": "wire", "width": "" }, { "direction": "out", "name": "p_l", "type": "wire", "width": "" }, { "direction": "in", "name": "pm1_l", "type": "wire", "width": "" }, { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "head", "type": "wire", "width": "" }, { "direction": "in", "name": "b_in", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "b16", "type": "wire", "width": "" }, { "direction": "in", "name": "x", "type": "wire", "width": "" } ], "mul_array2": [ { "direction": "in", "name": "rs1_l", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "rs2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "valid", "type": "wire", "width": "" }, { "direction": "in", "name": "areg", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "accreg", "type": "wire", "width": "[135:129]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_step", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[135:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "mux", "type": "wire", "width": "" }, { "direction": "in", "name": "bot", "type": "wire", "width": "" }, { "direction": "out", "name": "cout", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "sum", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "b6", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b3", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b8", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b2", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b1", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b7", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "b0", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b4", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b5", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "pcoutx2", "type": "wire", "width": "" }, { "direction": "out", "name": "psum", "type": "wire", "width": "[98:0]" }, { "direction": "out", "name": "pcout", "type": "wire", "width": "[98:0]" }, { "direction": "in", "name": "a1c", "type": "wire", "width": "[81:4]" }, { "direction": "in", "name": "pc", "type": "wire", "width": "[98:30]" }, { "direction": "in", "name": "ps", "type": "wire", "width": "[98:31]" }, { "direction": "in", "name": "a0s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a1s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a0c", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "n0", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "p0_l", "type": "wire", "width": "" }, { "direction": "in", "name": "am1", "type": "wire", "width": "" }, { "direction": "in", "name": "am2", "type": "wire", "width": "" }, { "direction": "out", "name": "p_l", "type": "wire", "width": "" }, { "direction": "in", "name": "pm1_l", "type": "wire", "width": "" }, { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "head", "type": "wire", "width": "" }, { "direction": "in", "name": "b_in", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "b16", "type": "wire", "width": "" }, { "direction": "in", "name": "x", "type": "wire", "width": "" } ], "mul_bodec": [ { "direction": "in", "name": "rs1_l", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "rs2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "valid", "type": "wire", "width": "" }, { "direction": "in", "name": "areg", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "accreg", "type": "wire", "width": "[135:129]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_step", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[135:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "mux", "type": "wire", "width": "" }, { "direction": "in", "name": "bot", "type": "wire", "width": "" }, { "direction": "out", "name": "cout", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "sum", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "b6", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b3", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b8", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b2", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b1", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b7", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": 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"" }, { "direction": "out", "name": "cout", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "sum", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "b6", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b3", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b8", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b2", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b1", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b7", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "b0", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b4", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b5", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "pcoutx2", "type": "wire", "width": "" }, { "direction": "out", "name": "psum", "type": "wire", "width": "[98:0]" }, { "direction": "out", "name": "pcout", "type": "wire", "width": "[98:0]" }, { "direction": "in", "name": "a1c", "type": "wire", "width": "[81:4]" }, { "direction": "in", "name": "pc", "type": "wire", "width": "[98:30]" }, { "direction": "in", "name": "ps", "type": "wire", "width": "[98:31]" }, { "direction": "in", "name": "a0s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a1s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a0c", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "n0", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "p0_l", "type": "wire", "width": "" }, { "direction": "in", "name": "am1", "type": "wire", "width": "" }, { "direction": "in", "name": "am2", "type": "wire", "width": "" }, { "direction": "out", "name": "p_l", "type": "wire", "width": "" }, { "direction": "in", "name": "pm1_l", "type": "wire", "width": "" }, { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "head", "type": "wire", "width": "" }, { "direction": "in", "name": "b_in", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "b16", "type": "wire", "width": "" }, { "direction": "in", "name": "x", "type": "wire", "width": "" } ], "mul_ppgensign": [ { "direction": "in", "name": "rs1_l", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "rs2", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "valid", "type": "wire", "width": "" }, { "direction": "in", "name": "areg", "type": "wire", "width": "[96:0]" }, { "direction": "in", "name": "accreg", "type": "wire", "width": "[135:129]" }, { "direction": "in", "name": "x2", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "mul_step", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[135:0]" }, { "direction": "in", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "mux", "type": "wire", "width": "" }, { "direction": "in", "name": "bot", "type": "wire", "width": "" }, { "direction": "out", "name": "cout", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "sum", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "b6", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b3", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b8", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b2", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b1", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b7", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "a", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "b0", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b4", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "b5", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "pcoutx2", "type": "wire", "width": "" }, { "direction": "out", "name": "psum", "type": "wire", "width": "[98:0]" }, { "direction": "out", "name": "pcout", "type": "wire", "width": "[98:0]" }, { "direction": "in", "name": "a1c", "type": "wire", "width": "[81:4]" }, { "direction": "in", "name": "pc", "type": "wire", "width": "[98:30]" }, { "direction": "in", "name": "ps", "type": "wire", "width": "[98:31]" }, { "direction": "in", "name": "a0s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a1s", "type": "wire", "width": "[81:0]" }, { "direction": "in", "name": "a0c", "type": "wire", "width": "[81:4]" }, { "direction": "out", "name": "n0", "type": "wire", "width": "" }, { "direction": "in", "name": "b", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "p0_l", "type": "wire", "width": "" }, { "direction": "in", "name": "am1", "type": "wire", "width": "" }, { "direction": "in", "name": "am2", "type": "wire", "width": "" }, { "direction": "out", "name": "p_l", "type": "wire", "width": "" }, { "direction": "in", "name": "pm1_l", "type": "wire", "width": "" }, { "direction": "out", "name": "z", "type": "wire", "width": "" }, { "direction": "in", "name": "d0", "type": "wire", "width": "" }, { "direction": "in", "name": "head", "type": "wire", "width": "" }, { "direction": "in", "name": "b_in", "type": "wire", "width": "[63:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "b16", "type": "wire", "width": "" }, { "direction": "in", "name": "x", "type": "wire", "width": "" } ], "mux2ds": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "mux3ds": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "mux4ds": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "os2wb": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rstn", "type": "wire", "width": "" }, { "direction": "in", "name": "pcx_req", "type": "wire", "width": "[ 4:0]" }, { "direction": "in", "name": "pcx_atom", "type": "wire", "width": "" }, { "direction": "in", "name": "pcx_data", "type": "wire", "width": "[123:0]" }, { "direction": "out", "name": "pcx_grant", "type": "wire", "width": "[ 4:0]" }, { "direction": "out", "name": "cpx_ready", "type": "wire", "width": "" }, { "direction": "out", "name": "cpx_packet", "type": "wire", "width": "[144:0]" }, { "direction": "in", "name": "wb_data_i", "type": "wire", "width": "[ 63:0]" }, { "direction": "in", "name": "wb_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_cycle", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_strobe", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_we", "type": "wire", "width": "" }, { "direction": "out", "name": "wb_sel", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "wb_addr", "type": "wire", "width": "[ 63:0]" }, { "direction": "out", "name": "wb_data_o", "type": "wire", "width": "[ 63:0]" }, { "direction": "out", "name": "fp_pcx", "type": "wire", "width": "[123:0]" }, { "direction": "out", "name": "fp_req", "type": "wire", "width": "" }, { "direction": "in", "name": "fp_cpx", "type": "wire", "width": "[144:0]" }, { "direction": "in", "name": "fp_rdy", "type": "wire", "width": "" }, { "direction": "in", "name": "eth_int", "type": "wire", "width": "" }, { "direction": "out", "name": "will", "type": "wire", "width": "" } ], "sink": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "source": [ { "direction": "in", "name": "din", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "input", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "en", "type": "wire", "width": "" }, { "direction": "out", "name": "dout", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in0", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "in1", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel0", "type": "wire", "width": "" }, { "direction": "in", "name": "sel1", "type": "wire", "width": "" }, { "direction": "in", "name": "in2", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel2", "type": "wire", "width": "" }, { "direction": "in", "name": "in3", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "in", "name": "sel3", "type": "wire", "width": "" }, { "direction": "in", "name": "PORTS", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[SIZE-1:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "set_l", "type": "wire", "width": "" }, { "direction": "in", "name": "clkl", "type": "wire", "width": "" } ], "spc_pcx_buf": [ { "direction": "in", "name": "spc_pcx_data_pa_buf", "type": "wire", "width": "[`PCX_WIDTH-1:0]" }, { "direction": "in", "name": "spc_pcx_atom_pq_buf", "type": "wire", "width": "" }, { "direction": "in", "name": "spc_pcx_req_pq_buf", "type": "wire", "width": "[4:0]" }, { "direction": "in", "name": "pcx_spc_grant_px", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "spc_pcx_data_pa", "type": "wire", "width": "[`PCX_WIDTH-1:0]" }, { "direction": "out", "name": "spc_pcx_atom_pq", "type": "wire", "width": "" }, { "direction": "out", "name": "spc_pcx_req_pq", "type": "wire", "width": "[4:0]" }, { "direction": "out", "name": "pcx_spc_grant_px_buf", "type": "wire", "width": "[4:0]" } ], "sync_pulse_synchronizer": [ { "direction": "out", "name": "sync_out", "type": "wire", "width": "" }, { "direction": "out", "name": "so", "type": "wire", "width": "" }, { "direction": "in", "name": "async_in", "type": "wire", "width": "" }, { "direction": "in", "name": "gclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "si", "type": "wire", "width": "" }, { "direction": "in", "name": "se", "type": "wire", "width": "" } ], "ucb_flow_2buf": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_data", "type": "wire", "width": "[IOB_UCB_WIDTH-1:0]" }, { "direction": "out", "name": "ucb_iob_stall", "type": "wire", "width": "" }, { "direction": "out", "name": "rd_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "thr_id_in", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "out", "name": "buf_id_in", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "out", "name": "size_in", "type": "wire", "width": "[`UCB_SIZE_HI-`UCB_SIZE_LO:0]" }, { "direction": "out", "name": "addr_in", "type": "wire", "width": "[`UCB_ADDR_HI-`UCB_ADDR_LO:0]" }, { "direction": "out", "name": "data_in", "type": "wire", "width": "[`UCB_DATA_HI-`UCB_DATA_LO:0]" }, { "direction": "in", "name": "req_acpted", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_ack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_nack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_id_out", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "buf_id_out", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "in", "name": "data128", "type": "wire", "width": "" }, { "direction": "in", "name": "data_out", "type": "wire", "width": "[REG_WIDTH-1:0]" }, { "direction": "out", "name": "ack_busy", "type": "wire", "width": "" }, { "direction": "in", "name": "int_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "int_typ", "type": "wire", "width": "[`UCB_PKT_HI-`UCB_PKT_LO:0]" }, { "direction": "in", "name": "int_thr_id", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "dev_id", "type": "wire", "width": "[`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0]" }, { "direction": "in", "name": "int_stat", "type": "wire", "width": "[`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0]" }, { "direction": "in", "name": "int_vec", "type": "wire", "width": "[`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0]" }, { "direction": "out", "name": "int_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_data", "type": "wire", "width": "[UCB_IOB_WIDTH-1:0]" }, { "direction": "in", "name": "iob_ucb_stall", "type": "wire", "width": "" } ], "ucb_flow_jbi": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_data", "type": "wire", "width": "[IOB_UCB_WIDTH-1:0]" }, { "direction": "out", "name": "ucb_iob_stall", "type": "wire", "width": "" }, { "direction": "out", "name": "rd_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "thr_id_in", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "out", "name": "buf_id_in", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "out", "name": "size_in", "type": "wire", "width": "[`UCB_SIZE_HI-`UCB_SIZE_LO:0]" }, { "direction": "out", "name": "addr_in", "type": "wire", "width": "[`UCB_ADDR_HI-`UCB_ADDR_LO:0]" }, { "direction": "out", "name": "data_in", "type": "wire", "width": "[`UCB_DATA_HI-`UCB_DATA_LO:0]" }, { "direction": "in", "name": "req_acpted", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_ack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_nack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_id_out", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "buf_id_out", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "in", "name": "data128", "type": "wire", "width": "" }, { "direction": "in", "name": "data_out", "type": "wire", "width": "[REG_WIDTH-1:0]" }, { "direction": "out", "name": "ack_busy", "type": "wire", "width": "" }, { "direction": "in", "name": "int_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "int_typ", "type": "wire", "width": "[`UCB_PKT_HI-`UCB_PKT_LO:0]" }, { "direction": "in", "name": "int_thr_id", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "dev_id", "type": "wire", "width": "[`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0]" }, { "direction": "in", "name": "int_stat", "type": "wire", "width": "[`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0]" }, { "direction": "in", "name": "int_vec", "type": "wire", "width": "[`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0]" }, { "direction": "out", "name": "int_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_data", "type": "wire", "width": "[UCB_IOB_WIDTH-1:0]" }, { "direction": "in", "name": "iob_ucb_stall", "type": "wire", "width": "" } ], "ucb_flow_spi": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_data", "type": "wire", "width": "[IOB_UCB_WIDTH-1:0]" }, { "direction": "out", "name": "ucb_iob_stall", "type": "wire", "width": "" }, { "direction": "out", "name": "rd_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "ifill_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "thr_id_in", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "out", "name": "buf_id_in", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "out", "name": "size_in", "type": "wire", "width": "[`UCB_SIZE_HI-`UCB_SIZE_LO:0]" }, { "direction": "out", "name": "addr_in", "type": "wire", "width": "[`UCB_ADDR_HI-`UCB_ADDR_LO:0]" }, { "direction": "out", "name": "data_in", "type": "wire", "width": "[`UCB_DATA_HI-`UCB_DATA_LO:0]" }, { "direction": "in", "name": "req_acpted", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_ack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_nack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "ifill_ack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "ifill_nack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_id_out", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "buf_id_out", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "in", "name": "data128", "type": "wire", "width": "" }, { "direction": "in", "name": "data_out", "type": "wire", "width": "[REG_WIDTH-1:0]" }, { "direction": "out", "name": "ack_busy", "type": "wire", "width": "" }, { "direction": "in", "name": "int_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "int_typ", "type": "wire", "width": "[`UCB_PKT_HI-`UCB_PKT_LO:0]" }, { "direction": "in", "name": "int_thr_id", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "dev_id", "type": "wire", "width": "[`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0]" }, { "direction": "in", "name": "int_stat", "type": "wire", "width": "[`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0]" }, { "direction": "in", "name": "int_vec", "type": "wire", "width": "[`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0]" }, { "direction": "out", "name": "int_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_data", "type": "wire", "width": "[UCB_IOB_WIDTH-1:0]" }, { "direction": "in", "name": "iob_ucb_stall", "type": "wire", "width": "" } ], "ucb_noflow": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_l", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "iob_ucb_data", "type": "wire", "width": "[IOB_UCB_WIDTH-1:0]" }, { "direction": "out", "name": "ucb_iob_stall", "type": "wire", "width": "" }, { "direction": "out", "name": "rd_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_req_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "thr_id_in", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "out", "name": "buf_id_in", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "out", "name": "size_in", "type": "wire", "width": "[`UCB_SIZE_HI-`UCB_SIZE_LO:0]" }, { "direction": "out", "name": "addr_in", "type": "wire", "width": "[`UCB_ADDR_HI-`UCB_ADDR_LO:0]" }, { "direction": "out", "name": "data_in", "type": "wire", "width": "[`UCB_DATA_HI-`UCB_DATA_LO:0]" }, { "direction": "in", "name": "rd_ack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "rd_nack_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "thr_id_out", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "buf_id_out", "type": "wire", "width": "[`UCB_BUF_HI-`UCB_BUF_LO:0]" }, { "direction": "in", "name": "data128", "type": "wire", "width": "" }, { "direction": "in", "name": "data_out", "type": "wire", "width": "[REG_WIDTH-1:0]" }, { "direction": "in", "name": "int_vld", "type": "wire", "width": "" }, { "direction": "in", "name": "int_typ", "type": "wire", "width": "[`UCB_PKT_HI-`UCB_PKT_LO:0]" }, { "direction": "in", "name": "int_thr_id", "type": "wire", "width": "[`UCB_THR_HI-`UCB_THR_LO:0]" }, { "direction": "in", "name": "dev_id", "type": "wire", "width": "[`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0]" }, { "direction": "in", "name": "int_stat", "type": "wire", "width": "[`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0]" }, { "direction": "in", "name": "int_vec", "type": "wire", "width": "[`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0]" }, { "direction": "out", "name": "int_busy", "type": "wire", "width": "" }, { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_vld", "type": "wire", "width": "" }, { "direction": "out", "name": "ucb_iob_data", "type": "wire", "width": "[UCB_IOB_WIDTH-1:0]" }, { "direction": "in", "name": "iob_ucb_stall", "type": "wire", "width": "" } ] }, "top_modules": [ "W1", "bw_r_cm16x40", "bw_r_cm16x40b", "bw_r_dcm", "bw_r_efa", "bw_r_idct_array", "bw_r_irf_72_4x1_mux", "bw_r_irf_core", "bw_r_irf_register", "bw_r_l2d", "bw_r_l2t", "bw_r_l2t_subbank", "bw_r_rf16x128d", "bw_r_rf16x2", "bw_r_rf32x108", "bw_r_tlb_data_ram", "bw_r_tlb_data_ram_fpga", "bw_r_tlb_tag_ram", "bw_r_tlb_tag_ram_fpga", "bw_rf_16x65", "bw_rf_16x81", "cluster_header_ctu", "cluster_header_dup", "cluster_header_sync", "dbl_buf", "dcm_panel", "dcm_panel_pair", "dff_ns", "dff_s", "dff_sscan", "dffe_ns", "dffe_s", "dffr_async", "dffr_async_ns", "dffr_async_ns_cl_r1", "dffr_async_ns_r1", "dffr_ns", "dffr_ns_r1", "dffr_s", "dffre_ns", "dffre_s", "dffrl_async", "dffrl_async_ns", "dffrl_ns", "dffrl_s", "dffrle_ns", "dffrle_s", "dffsl_async_ns", "dffsl_ns", "dp_mux2es", "dp_mux3ds", "dp_mux4ds", "dp_mux5ds", "dp_mux8ds", "eth_cop", "fpu_bufrpt_grp64", "fpu_rptr_fp_cpx_grp16", "fpu_rptr_inq", "fpu_rptr_pcx_fpio_grp16", "lsu", "mul_array1", "mul_array2", "mul_bodec", "mul_booth", "mul_csa32", "mul_csa42", "mul_ha", "mul_mux2", "mul_negen", "mul_ppgen", "mul_ppgen3", "mul_ppgen3lsb4", "mul_ppgen3sign", "mul_ppgenrow3", "mul_ppgensign", "mux2ds", "mux3ds", "mux4ds", "os2wb", "sink", "source", "spc_pcx_buf", "sync_pulse_synchronizer", "ucb_flow_2buf", "ucb_flow_jbi", "ucb_flow_spi", "ucb_noflow" ] }, { "namespace": "opencores", "name": "srl_fifo", "latest": "master", "versions": [ "master" ], "description": "Xilinx SRL16/SRL32-based compact FIFO \u2014 uses SRL shift-register primitives for storage on Xilinx FPGA targets. VHDL utility primitive.", "license": "LGPL-2.1-or-later", "language": "vhdl-2008", "library": "work", "source_url": "https://github.com/freecores/srl_fifo.git", "tags": [ "16", "32", "64", "buffer", "fifo", "queue", "srl" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T10:26:01Z", "updated_at": "2009-03-10T09:35:24+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "verdict", "top_ports": { "srl_fifo_16": [ { "direction": "in", "name": "data_in", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "out", "name": "data_out", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "write", "type": "std_logic", "width": "" }, { "direction": "in", "name": "read", "type": "std_logic", "width": "" }, { "direction": "out", "name": "full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "half_full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "data_present", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk", "type": "std_logic", "width": "" } ], "srl_fifo_32": [ { "direction": "in", "name": "data_in", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "out", "name": "data_out", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "write", "type": "std_logic", "width": "" }, { "direction": "in", "name": "read", "type": "std_logic", "width": "" }, { "direction": "out", "name": "full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "half_full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "data_present", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk", "type": "std_logic", "width": "" } ], "srl_fifo_64": [ { "direction": "in", "name": "data_in", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "out", "name": "data_out", "type": "std_logic_vector", "width": "width -1 downto 0" }, { "direction": "in", "name": "reset", "type": "std_logic", "width": "" }, { "direction": "in", "name": "write", "type": "std_logic", "width": "" }, { "direction": "in", "name": "read", "type": "std_logic", "width": "" }, { "direction": "out", "name": "full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "half_full", "type": "std_logic", "width": "" }, { "direction": "out", "name": "data_present", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk", "type": "std_logic", "width": "" } ] }, "top_modules": [ "srl_fifo_16", "srl_fifo_32", "srl_fifo_64" ] }, { "namespace": "opencores", "name": "storm_soc", "latest": "master", "versions": [ "master" ], "description": "Educational SoC with peripheral suite \u2014 I2C, UART, PS/2, PWM, 7-segment display, SPI, SRAM controller, timer, and vectored interrupt controller. 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"type": "wire", "width": "" }, { "direction": "in", "name": "ctrl", "type": "wire", "width": "[10:0]" }, { "direction": "in", "name": "d0", "type": "wire", "width": "[197:0]" }, { "direction": "in", "name": "d1", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "B", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "C", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "in", "name": "d", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "A", "type": "wire", "width": "[`WIDTH:0]" } ], "mod_p": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "reset", "type": "wire", "width": "" }, { "direction": "in", "name": "ctrl", "type": "wire", "width": "[10:0]" }, { "direction": "in", "name": "d0", "type": "wire", "width": "[197:0]" }, { "direction": "in", "name": "d1", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "B", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "out", "name": "C", "type": "wire", "width": "[`WIDTH:0]" }, { "direction": "in", "name": "d", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "A", "type": "wire", "width": "[`WIDTH:0]" } ], "pairing": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "reset", "type": "wire", "width": "" }, { "direction": "in", "name": "sel", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "w", "type": "wire", "width": "" }, { "direction": "in", "name": "update", "type": "wire", "width": "" }, { "direction": "in", "name": "ready", "type": "wire", "width": "" }, { "direction": "in", "name": "i", "type": "wire", "width": "" }, { "direction": "out", "name": "o", "type": "wire", "width": "" }, { "direction": "out", "name": "done", "type": "wire", "width": "" } ], "select": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sel", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "w", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "[197:0]" }, { "direction": "out", "name": "out", "type": "wire", "width": "[197:0]" }, { "direction": "out", "name": "done", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_in", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "addr_fsm_in", "type": "wire", "width": "[5:0]" }, { "direction": "in", "name": "w_in", "type": "wire", "width": "" }, { "direction": "out", "name": "addr_out", "type": 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"out", "name": "addr_out", "type": "wire", "width": "[5:0]" }, { "direction": "out", "name": "w_out", "type": "wire", "width": "" }, { "direction": "in", "name": "from_ram", "type": "wire", "width": "[197:0]" }, { "direction": "in", "name": "const_effective", "type": "wire", "width": "" } ], "v1": [ { "direction": "in", "name": "a", "type": "wire", "width": "[193:0]" }, { "direction": "out", "name": "c", "type": "wire", "width": "[193:0]" } ], "v2": [ { "direction": "in", "name": "a", "type": "wire", "width": "[193:0]" }, { "direction": "out", "name": "c", "type": "wire", "width": "[193:0]" } ], "v3": [ { "direction": "in", "name": "a", "type": "wire", "width": "[1005:0]" }, { "direction": "out", "name": "c", "type": "wire", "width": "[1005:0]" } ] }, "top_modules": [ "PPG", "const_", "f3_add", "f3_mult", "f3_sub", "f3m_add", "mod_p", "pairing", "select", "tiny", "v1", "v2", "v3" ] }, { "namespace": "opencores", "name": "trigonometric_functions_in_double_fpu", "latest": "master", "versions": [ "master" ], "description": "Trigonometric functions using double precision Floating Point Unit ////", "license": "OpenCores-Permissive-1.0", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/trigonometric_functions_in_double_fpu.git", "tags": [ "cosecant", "cosine", "cotangent", "lut", "secant", "sine", "tangent" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T10:26:01Z", "updated_at": "2013-07-18T15:04:17+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "header", "top_ports": { "cosecant_lut": [ { "direction": "in", "name": "quad", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "degrees", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "data", "type": "wire", "width": "[63:0]" } ], "cosine_lut": [ { "direction": "in", "name": "quad", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "degrees", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "data", "type": "wire", "width": "[63:0]" } ], "cotangent_lut": [ { "direction": "in", "name": "quad", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "degrees", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "data", "type": "wire", "width": "[63:0]" } ], "dividor": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "inp", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "out", "name": "out", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" } ], "secant_lut": [ { "direction": "in", "name": "quad", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "degrees", "type": "wire", "width": "[`INPUT_WIDTH-1:0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "out", "name": "data", "type": "wire", "width": "[63:0]" } ], "sine_lut": [ { "direction": "in", "name": "quad", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", 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"direction": "in", "name": "address_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "strobe_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVP", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVM", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOE_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" } ], "usbHostCyc2Wrap_usb1t11": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "strobe_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVPin", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVMin", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVPout", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVMout", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOE_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" } ], "usbHostSlaveAvalonWrap": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "reset", "type": "wire", "width": "" }, { "direction": "in", "name": "address", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "writedata", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "readdata", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "write", "type": "wire", "width": "" }, { "direction": "in", "name": "read", "type": "wire", "width": "" }, { "direction": "out", "name": "waitrequest", "type": "wire", "width": "" }, { "direction": "in", "name": "chipselect", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVPI", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVMI", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVPO", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVMO", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireDataOutTick", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireDataInTick", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOutEn_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" } ], "usbHostSlaveCyc2Wrap": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "strobe_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVP", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVM", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOE_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" } ], "usbSlaveCyc2Wrap": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "strobe_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVP", "type": "wire", "width": "" }, { "direction": "inout", "name": "USBWireVM", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOE_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" }, { "direction": "out", "name": "USBDPlusPullup", "type": "wire", "width": "" }, { "direction": "out", "name": "USBDMinusPullup", "type": "wire", "width": "" }, { "direction": "in", "name": "vBusDetect", "type": "wire", "width": "" } ], "usbSlaveCyc2Wrap_usb1t11": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_i", "type": "wire", "width": "" }, { "direction": "in", "name": "address_i", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "strobe_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "irq", "type": "wire", "width": "" }, { "direction": "in", "name": "usbClk", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVPin", "type": "wire", "width": "" }, { "direction": "in", "name": "USBWireVMin", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVPout", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireVMout", "type": "wire", "width": "" }, { "direction": "out", "name": "USBWireOE_n", "type": "wire", "width": "" }, { "direction": "out", "name": "USBFullSpeed", "type": "wire", "width": "" }, { "direction": "out", "name": "USBDPlusPullup", "type": "wire", "width": "" }, { "direction": "out", "name": "USBDMinusPullup", "type": "wire", "width": "" }, { "direction": "in", "name": "vBusDetect", "type": "wire", "width": "" } ] }, "top_modules": [ "speedCtrlMux", "testCase0", "usbDeviceActelTop", "usbDeviceAlteraTop", "usbDeviceXilinxTop", "usbHostCyc2Wrap", "usbHostCyc2Wrap_usb1t11", "usbHostSlaveAvalonWrap", "usbHostSlaveCyc2Wrap", "usbSlaveCyc2Wrap", "usbSlaveCyc2Wrap_usb1t11" ] }, { "namespace": "opencores", "name": "versatile_fifo", "latest": "master", "versions": [ "master" ], "description": "Generic parameterized FIFO library covering single-clock and dual-clock variants with optional almost-full/almost-empty thresholds.", "license": "LGPL-2.1-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/freecores/versatile_fifo.git", "tags": [ "access", "async", "asynchronous", "buffer", "comparator", "dual", "memory", "queue", "random", "simplex", "versatile", "vfifo" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T23:36:17Z", "updated_at": "2010-11-04T10:02:53+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "top_ports": { "async_fifo_dw_simplex_top": [ { "direction": "in", "name": "a_d", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "in", "name": "a_wr", "type": "wire", "width": "" }, { "direction": "out", "name": "a_fifo_full", "type": "wire", "width": "" }, { "direction": "out", "name": "a_q", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "in", "name": "a_rd", "type": "wire", "width": "" }, { "direction": "out", "name": "a_fifo_empty", "type": "wire", "width": "" }, { "direction": "in", "name": "a_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "a_rst", "type": "wire", "width": "" }, { "direction": "in", "name": "b_d", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "in", "name": "b_wr", "type": "wire", "width": "" }, { "direction": "out", "name": "b_fifo_full", "type": "wire", "width": "" }, { "direction": "out", "name": "b_q", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "in", "name": "b_rd", "type": "wire", "width": "" }, { "direction": "out", "name": "b_fifo_empty", "type": "wire", "width": "" }, { "direction": "in", "name": "b_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "b_rst", "type": "wire", "width": "" } ], "async_fifo_mq": [ { "direction": "in", "name": "d", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "out", "name": "fifo_full", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "write", "type": "wire", "width": "" }, { "direction": "in", "name": "write_enable", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "rst1", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "out", "name": "fifo_empty", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "read", "type": "wire", "width": "" }, { "direction": "in", "name": "read_enable", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "clk2", "type": "wire", "width": "" }, { "direction": "in", "name": "rst2", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "[0:nr_of_queues-1]" } ], "async_fifo_mq_md": [ { "direction": "in", "name": "d", "type": "wire", "width": "[data_width*nr_of_queues-1:0]" }, { "direction": "out", "name": "fifo_full", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "write", "type": "wire", "width": "" }, { "direction": "in", "name": "write_enable", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "clk1", "type": "wire", "width": "" }, { "direction": "in", "name": "rst1", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[data_width-1:0]" }, { "direction": "out", "name": "fifo_empty", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "read", "type": "wire", "width": "" }, { "direction": "in", "name": "read_enable", "type": "wire", "width": "[0:nr_of_queues-1]" }, { "direction": "in", "name": "clk2", "type": "wire", "width": "" }, { "direction": "in", "name": "rst2", "type": "wire", "width": "" }, { "direction": "in", "name": "a", "type": "wire", "width": "[0:nr_of_queues-1]" } ], "sd_fifo": [ { "direction": "in", "name": "wb_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "wb_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "wb_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "wb_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_adr_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "sd_dat_i", "type": "wire", "width": "[7:0]" }, { "direction": "out", "name": "sd_dat_o", "type": "wire", "width": "[7:0]" }, { "direction": "in", "name": "sd_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_re_i", "type": "wire", "width": "" }, { "direction": "in", "name": "sd_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "fifo_full", "type": "wire", "width": "[1:4]" }, { "direction": "out", "name": "fifo_empty", "type": "wire", "width": "[1:4]" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" } ], "vfifo_dual_port_ram_": [ { "direction": "in", "name": "d_a", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "adr_a", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "adr_b", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "we_a", "type": "wire", "width": "" }, { "direction": "out", "name": "q_b", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "d_b", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "out", "name": "q_a", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "we_b", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_a", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" } ], "vfifo_dual_port_ram_sc_dw": [ { "direction": "in", "name": "d_a", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "adr_a", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "adr_b", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "we_a", "type": "wire", "width": "" }, { "direction": "out", "name": "q_b", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "d_b", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "out", "name": "q_a", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "we_b", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" } ], "vfifo_dual_port_ram_sc_sw": [ { "direction": "in", "name": "d_a", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "adr_a", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "adr_b", "type": "wire", "width": "[(ADDR_WIDTH-1):0]" }, { "direction": "in", "name": "we_a", "type": "wire", "width": "" }, { "direction": "out", "name": "q_b", "type": "wire", "width": "[(DATA_WIDTH-1):0]" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" } ] }, "top_modules": [ "async_fifo_dw_simplex_top", "async_fifo_mq", "async_fifo_mq_md", "sd_fifo", "vfifo_dual_port_ram_", "vfifo_dual_port_ram_sc_dw", "vfifo_dual_port_ram_sc_sw" ] }, { "namespace": "opencores", "name": "vga_lcd", "latest": "master", "versions": [ "master" ], "description": "VGA + LCD display controller generating timing for standard VGA modes and parallel LCD interfaces. Includes pixel clock generator and frame buffer interface.", "license": "GPL-2.0-or-later", "language": "verilog", "library": "count", "source_url": "https://github.com/freecores/vga_lcd.git", "tags": [ "access", "altera", "buffer", "clkgen", "colproc", "counter", "curproc", "datapath", "master", "memory", "ported", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-03T23:36:17Z", "updated_at": "2003-09-23T13:09:26+00:00", "health_tier": "bronze", "last_verified_at": "2026-05-04", "desc_source": "verdict", "provides_packages": [ "count" ], "top_ports": { "Pgen": [ { "direction": "in", "name": "mclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ctrl_Ven", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ctrl_HSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Thsync", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Thgdel", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Thgate", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "Thlen", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "ctrl_VSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Tvsync", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Tvgdel", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Tvgate", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "Tvlen", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "ctrl_CSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ctrl_BlankL", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eoh", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eov", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Gate", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Hsync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Vsync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Csync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Blank", "type": "std_logic", "width": "" } ], "Tgen": [ { "direction": "in", "name": "clk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst", "type": "std_logic", "width": "" }, { "direction": "in", "name": "HSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Thsync", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Thgdel", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Thgate", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "Thlen", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "VSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "Tvsync", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Tvgdel", "type": "unsigned", "width": "7 downto 0" }, { "direction": "in", "name": "Tvgate", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "Tvlen", "type": "unsigned", "width": "15 downto 0" }, { "direction": "in", "name": "CSyncL", "type": "std_logic", "width": "" }, { "direction": "in", "name": "BlankL", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eol", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eof", "type": "std_logic", "width": "" }, { "direction": "out", "name": "gate", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Hsync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Vsync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Csync", "type": "std_logic", "width": "" }, { "direction": "out", "name": "Blank", "type": "std_logic", "width": "" } ], "generic_dpram": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rrst", "type": "wire", "width": "" }, { "direction": "in", "name": "rce", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrst", "type": "wire", "width": "" }, { "direction": "in", "name": "wce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "waddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "register", "type": "wire", "width": "" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "start", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "finish", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "wraddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "rdaddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclock", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclocken", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclock", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclocken", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "CLKA", "type": "wire", "width": "" }, { "direction": "in", "name": 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"width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "address", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "inclock", "type": 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"direction": "in", "name": "CLUT_STB_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CYC_I", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ACK_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ERR_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "unsigned", "width": "31 downto 2" }, { "direction": "in", "name": "MDAT_I", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "SEL_O", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "WE_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "STB_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CAB_O", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ERR_I", "type": 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"direction": "out", "name": "output", "type": "wire", "width": "" }, { "direction": "in", "name": "wbs_we_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wbm_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_bte_o", "type": "wire", "width": "[ 1:0]" }, { "direction": "in", "name": "wbm_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_p_i", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_pclk_p_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_pclk_m_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_hsync_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_vsync_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_de_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dvi_d_o", "type": "wire", "width": "[11:0]" }, { "direction": "out", "name": "clk_p_o", "type": "wire", "width": "" }, { "direction": "out", "name": "vsync_pad_o", "type": "wire", "width": "" }, { "direction": "out", "name": "csync_pad_o", "type": "wire", "width": "" }, { "direction": "out", "name": "blank_pad_o", "type": "wire", "width": "" }, { "direction": "out", "name": "r_pad_o", "type": "wire", "width": "[ 7:0]" }, { "direction": "out", "name": "data", "type": "wire", "width": "" } ], "vid_mem": [ { "direction": "in", "name": "CLK_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "RST_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "NRESET", "type": "std_logic", "width": "" }, { "direction": "out", "name": "INTA_O", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ADR_I", "type": "unsigned", "width": "10 downto 2" }, { "direction": "in", "name": "SDAT_I", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "SDAT_O", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "SEL_I", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "WE_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "VGA_STB_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CLUT_STB_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CYC_I", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ACK_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ERR_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ADR_O", "type": "unsigned", "width": "31 downto 2" }, { "direction": "in", "name": "MDAT_I", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "SEL_O", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "WE_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "STB_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CYC_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CAB_O", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ACK_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ERR_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "PCLK", "type": "std_logic", "width": "" }, { "direction": "out", "name": "HSYNC", "type": "std_logic", "width": "" }, { "direction": "out", "name": "VSYNC", "type": "std_logic", "width": "" }, { "direction": "out", "name": "CSYNC", "type": "std_logic", "width": "" }, { "direction": "out", "name": "BLANK", "type": "std_logic", "width": "" }, { "direction": "out", "name": "R", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "G", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "B", "type": "std_logic_vector", "width": "7 downto 0" } ], "wb_host": [ { "direction": "in", "name": "CLK_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "RST_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "NRESET", "type": "std_logic", "width": "" }, { "direction": "out", "name": "INTA_O", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ADR_I", "type": "unsigned", "width": "10 downto 2" }, { "direction": "in", "name": "SDAT_I", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "SDAT_O", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "SEL_I", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "WE_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "VGA_STB_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CLUT_STB_I", "type": "std_logic", "width": "" }, { "direction": "in", "name": "CYC_I", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ACK_O", "type": "std_logic", "width": "" }, { "direction": "out", "name": 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"out", "name": "CSYNC", "type": "std_logic", "width": "" }, { "direction": "out", "name": "BLANK", "type": "std_logic", "width": "" }, { "direction": "out", "name": "R", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "G", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "B", "type": "std_logic_vector", "width": "7 downto 0" } ], "xilinx_ram_dp": [ { "direction": "in", "name": "rclk", "type": "wire", "width": "" }, { "direction": "in", "name": "rrst", "type": "wire", "width": "" }, { "direction": "in", "name": "rce", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "wclk", "type": "wire", "width": "" }, { "direction": "in", "name": "wrst", "type": "wire", "width": "" }, { "direction": "in", "name": "wce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "waddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "register", "type": "wire", "width": "" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "start", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "finish", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "wraddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "rdaddress", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "wren", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclock", "type": "wire", "width": "" }, { "direction": "in", "name": "wrclocken", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclock", "type": "wire", "width": "" }, { "direction": "in", "name": "rdclocken", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "CLKA", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTA", "type": "wire", "width": "" }, { "direction": "in", "name": "ENA", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRA", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEA", "type": "wire", "width": "" }, { "direction": "out", "name": "DOA", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "CLKB", "type": "wire", "width": "" }, { "direction": "in", "name": "RSTB", "type": "wire", "width": "" }, { "direction": "in", "name": "ENB", "type": "wire", "width": "" }, { "direction": "in", "name": "ADDRB", "type": "wire", "width": "[awidth-1:0]" }, { "direction": "in", "name": "DIB", "type": "wire", "width": "[dwidth-1:0]" }, { "direction": "in", "name": "WEB", "type": "wire", "width": "" }, { "direction": "out", "name": "DOB", "type": "wire", "width": "[dwidth-1:0]" } ], "xilinx_ram_sp": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst", "type": "wire", "width": "" }, { "direction": "in", "name": "ce", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "oe", "type": "wire", "width": "" }, { "direction": "out", "name": "enable", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "in", "name": "di", "type": "wire", "width": "[dw-1:0]" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "do", "type": "wire", "width": "[dw-1:0]" }, { "direction": "out", "name": "from", "type": "wire", "width": "" }, { "direction": "out", "name": "raddr", "type": "wire", "width": "[aw-1:0]" }, { "direction": "out", "name": "drivers", "type": "wire", "width": "" }, { "direction": "in", "name": "address", "type": "wire", "width": "[awidth -1:0]" }, { "direction": "in", "name": "inclock", "type": "wire", "width": "" }, { "direction": "out", "name": "q", "type": "wire", "width": "[dwidth -1:0]" }, { "direction": "in", "name": "en", "type": "wire", "width": "" } ] }, "top_modules": [ "Pgen", "Tgen", "generic_dpram", "generic_spram", "tst_bench", "ud_cnt", "vga_enh_top", "vid_mem", "wb_host", "xilinx_ram_dp", "xilinx_ram_sp" ] }, { "namespace": "opencores", "name": "video_stream_scaler", "latest": "master", "versions": [ "master" ], "description": "Video stream scaler \u2014 line-buffer-based filtering pipeline that resamples raster video streams to a target output resolution. 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"four", "type": "wire", "width": "" } ], "wb_lpc_periph": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "nrst_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_adr_o", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wbm_dat_o", "type": "wire", "width": "[31:0]" }, { "direction": "in", "name": "wbm_dat_i", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "wbm_sel_o", "type": "wire", "width": "[3:0]" }, { "direction": "out", "name": "wbm_tga_o", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "wbm_we_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_stb_o", "type": "wire", "width": "" }, { "direction": "out", "name": "wbm_cyc_o", "type": "wire", "width": "" }, { "direction": "in", "name": "wbm_ack_i", "type": "wire", "width": "" }, { "direction": "in", "name": "wbm_err_i", "type": "wire", "width": "" }, { "direction": "in", "name": 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"direction": "a", "name": "inter", "type": "k.a", "width": "" } ], "clint_sync_wedge": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rtc_i", "type": "wire", "width": "" }, { "direction": "out", "name": "timer_irq_o", "type": "wire", "width": "[NR_CORES-1:0]" }, { "direction": "out", "name": "ipi_o", "type": "wire", "width": "[NR_CORES-1:0]" }, { "direction": "in", "name": "through", "type": "wire", "width": "" }, { "direction": "in", "name": "serial_i", "type": "wire", "width": "" }, { "direction": "out", "name": "r_edge_o", "type": "wire", "width": "" }, { "direction": "out", "name": "f_edge_o", "type": "wire", "width": "" }, { "direction": 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{ "direction": "out", "name": "ddr4_ba", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "ddr4_bg", "type": "wire", "width": "[ 1:0]" }, { "direction": "out", "name": "ddr4_reset_n", "type": "wire", "width": "" }, { "direction": "out", "name": "ddr4_ck_p", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_ck_n", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_a", "type": "wire", "width": "[ 16:0]" }, { "direction": "out", "name": "ddr4_act_n", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_cke", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_cs_n", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_odt", "type": "wire", "width": "[ 0:0]" }, { "direction": "out", "name": "ddr4_par", "type": "wire", "width": "[ 0:0]" }, { "direction": "in", "name": "ddr4_alert_n", "type": "wire", "width": "[ 0:0]" }, { "direction": "in", "name": "oct_rzqin", "type": "wire", "width": "" }, { "direction": "out", "name": "led", "type": "wire", "width": "[ 3:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_ck", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_ck_n", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_a", "type": "wire", "width": "[16:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_act_n", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_ba", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_bg", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_cke", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_cs_n", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_odt", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_reset_n", "type": "wire", "width": "[0:0]" }, { "direction": "out", "name": "emif_hps_mem_mem_par", "type": "wire", "width": "[0:0]" }, { "direction": "in", "name": "emif_hps_mem_mem_alert_n", "type": "wire", "width": "[0:0]" }, { "direction": "in", "name": "emif_hps_oct_oct_rzqin", "type": "wire", "width": "" }, { "direction": "in", "name": "emif_hps_pll_ref_clk_p", "type": "wire", "width": "" }, { "direction": "inout", "name": "emif_hps_mem_mem_dbi_n", "type": "wire", "width": "[8-1:0]" }, { "direction": "inout", "name": "emif_hps_mem_mem_dq", "type": "wire", "width": "[64-1:0]" }, { "direction": "inout", "name": "emif_hps_mem_mem_dqs", "type": "wire", "width": "[8-1:0]" }, { "direction": "inout", "name": "emif_hps_mem_mem_dqs_n", "type": "wire", "width": "[8-1:0]" }, { "direction": "in", "name": "hps_jtag_tck", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_jtag_tms", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_jtag_tdo", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_jtag_tdi", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_sdmmc_CCLK", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_sdmmc_CMD", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_sdmmc_D0", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_sdmmc_D1", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_sdmmc_D2", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_sdmmc_D3", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TX_CLK", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RX_CLK", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TX_CTL", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RX_CTL", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TXD0", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TXD1", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RXD0", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RXD1", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TXD2", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_TXD3", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RXD2", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_emac0_RXD3", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_emac0_MDIO", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_emac0_MDC", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_uart0_RX", "type": "wire", "width": "" }, { "direction": "out", "name": "hps_uart0_TX", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_i2c1_SDA", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_i2c1_SCL", "type": "wire", "width": "" }, { "direction": "inout", "name": "hps_gpio1_io0", "type": "wire", "width": "" }, { "direction": "in", "name": "hps_ref_clk", "type": "wire", "width": "" }, { "direction": "333", "name": "MHz", "type": "33.333", "width": "" } ], "find_first_one": [ { "direction": "in", "name": "vector", "type": "wire", "width": "" }, { "direction": "in", "name": "in_i", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "first_one_o", "type": "wire", "width": "[$clog2(WIDTH)-1:0]" }, { "direction": "out", "name": "no_ones_o", "type": "wire", "width": "" } ], "hpdcache_sram_1rw": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "cs", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[ADDR_SIZE-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ], "hpdcache_sram_1rw_00000006_0000001c_00000040_00000001": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "cs", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[ADDR_SIZE-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "in", "name": "int", "type": "wire", "width": "" } ], "hpdcache_sram_wbyteenable_1rw": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "cs", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[ADDR_SIZE-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ], "hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "cs", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "in", "name": "addr", "type": "wire", "width": "[ADDR_SIZE-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "in", "name": "int", "type": "wire", "width": "" } ], "miss_handler": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "out", "name": "flush_ack_o", "type": "wire", "width": "" }, { "direction": "out", "name": "miss_o", "type": "wire", "width": "" }, { "direction": "in", "name": "busy_i", "type": "wire", "width": "" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" }, { "direction": "out", "name": "bypass_gnt_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "out", "name": "bypass_valid_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "out", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_rsp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "miss_gnt_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "out", "name": "active_serving_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "out", "name": "critical_word_o", "type": "wire", "width": "[63:0]" }, { "direction": "out", "name": "critical_word_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mshr_addr_matches_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "out", "name": "mshr_index_matches_o", "type": "wire", "width": "[NR_PORTS-1:0]" }, { "direction": "in", "name": "amo_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "amo_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "req_o", "type": "wire", "width": "[CVA6Cfg.DCACHE_SET_ASSOC-1:0]" }, { "direction": "out", "name": "addr_o", "type": "wire", "width": "[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]" }, { "direction": "out", "name": "cache_line_t", "type": "wire", "width": "" }, { "direction": "out", "name": "cl_be_t", "type": "wire", "width": "" }, { "direction": "out", "name": "we_o", "type": "wire", "width": "" }, { "direction": "in", "name": "in", "type": "wire", "width": "[CVA6Cfg.DCACHE_SET_ASSOC-1:0]" }, { "direction": "in", "name": "valid_dirty", "type": "wire", "width": "[CVA6Cfg.DCACHE_SET_ASSOC-1:0]" }, { "direction": "in", "name": "req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "rsp_t", "type": "wire", "width": "" } ], "riscv_peripherals": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_debug_noc2_data_i", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "in", "name": "buf_ariane_debug_noc2_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_debug_buf_noc2_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_debug_buf_noc3_data_o", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "out", "name": "ariane_debug_buf_noc3_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_debug_noc3_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_bootrom_noc2_data_i", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "in", "name": "buf_ariane_bootrom_noc2_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_bootrom_buf_noc2_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_bootrom_buf_noc3_data_o", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "out", "name": "ariane_bootrom_buf_noc3_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_bootrom_noc3_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_clint_noc2_data_i", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "in", "name": "buf_ariane_clint_noc2_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_clint_buf_noc2_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_clint_buf_noc3_data_o", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "out", "name": "ariane_clint_buf_noc3_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_clint_noc3_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_plic_noc2_data_i", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "in", "name": "buf_ariane_plic_noc2_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_plic_buf_noc2_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ariane_plic_buf_noc3_data_o", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "out", "name": "ariane_plic_buf_noc3_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "buf_ariane_plic_noc3_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ariane_boot_sel_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ndmreset_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dmactive_o", "type": "wire", "width": "" }, { "direction": "out", "name": "debug_req_o", "type": "wire", "width": "[NumHarts-1:0]" }, { "direction": "in", "name": "unavailable_i", "type": "wire", "width": "[NumHarts-1:0]" }, { "direction": "in", "name": "tck_i", "type": "wire", "width": "" }, { "direction": "in", "name": "tms_i", "type": "wire", "width": "" }, { "direction": "in", "name": "trst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "td_i", "type": "wire", "width": "" }, { "direction": "out", "name": "td_o", "type": "wire", "width": "" }, { "direction": "out", "name": "tdo_oe_o", "type": "wire", "width": "" }, { "direction": "in", "name": "rtc_i", "type": "wire", "width": "" }, { "direction": "out", "name": "timer_irq_o", "type": "wire", "width": "[NumHarts-1:0]" }, { "direction": "out", "name": "ipi_o", "type": "wire", "width": "[NumHarts-1:0]" }, { "direction": "in", "name": "irq_sources_i", "type": "wire", "width": "[NumSources-1:0]" }, { "direction": "in", "name": "irq_le_i", "type": "wire", "width": "[NumSources-1:0]" }, { "direction": "768", "name": "kHz", "type": "32.768", "width": "" }, { "direction": "a", "name": "inter", "type": "k.a", "width": "" } ], "tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "ports", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "[NumPorts-1:0]" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "[NumPorts-1:0]" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "be_t", "type": "wire", "width": "" } ] }, "top_modules": [ "amo_alu", "ariane_verilog_wrap", "ariane_xilinx", "clint_sync", "clint_sync_wedge", "cva6_altera", "find_first_one", "hpdcache_sram_1rw", "hpdcache_sram_1rw_00000006_0000001c_00000040_00000001", "hpdcache_sram_wbyteenable_1rw", "hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002", "miss_handler", "riscv_peripherals", "tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0" ] }, { "namespace": "openhwgroup", "name": "cve2", "latest": "e35390a7754f", "versions": [ "HEAD", "e35390a7754f", "0.0.0" ], "description": "CVE2 is a class of 2-stage pipeline OpenHW Foundation cores. Currently, the only core in this class is the CV32E20. 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"width": "" }, { "direction": "in", "name": "chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "ax_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ax_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ax_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ax_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "id_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "in", "name": "cnt_set_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cnt_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "cnt_dec_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cnt_req_i", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "cnt_gnt_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "alloc_req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "alloc_gnt_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_burst_unwrap_ax_chan", "latest": "master", "versions": [ "master" ], "description": "Wrapper with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "ax", "axi", "burst", "bus", "chan", "unwrap" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_burst_unwrap_ax_chan": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "ax_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ax_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "ax_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ax_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "id_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "in", "name": "cnt_set_err_i", "type": "wire", "width": "" }, { "direction": "out", "name": "cnt_err_o", "type": "wire", "width": "" }, { "direction": "in", "name": "cnt_dec_i", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "cnt_req_i", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "cnt_gnt_o", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "alloc_req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "alloc_gnt_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_cdc", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_cdc": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_cdc_dst", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "dst" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports" }, { "namespace": "pulp-platform", "name": "axi_cdc_dst_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "dst", "interface", "intf" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_cdc_dst_intf": [ { "direction": "in", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_aw_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_aw_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_w_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_w_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_slave_b_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_slave_b_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_ar_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_ar_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "r_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_slave_r_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_slave_r_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_cdc_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "interface", "intf" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_cdc_intf": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_cdc_src", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "src" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports" }, { "namespace": "pulp-platform", "name": "axi_cdc_src_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "interface", "intf", "src" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_cdc_src_intf": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_aw_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_aw_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_w_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_w_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_master_b_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_master_b_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_ar_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_ar_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "r_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_master_r_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_master_r_rptr_o", "type": "wire", "width": "[LogDepth:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_chan_compare", "latest": "master", "versions": [ "master" ], "description": "Compares AXI transactions between two independent clock domains for protocol compliance and equivalence.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "chan", "compare" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_chan_compare": [ { "direction": "in", "name": "clk_a_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_b_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "r_chan_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_chan_logger", "latest": "master", "versions": [ "master" ], "description": "Logs AXI protocol transactions across all five channels (AW, W, B, AR, R) with ready/valid handshake monitoring.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "chan", "logger" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "provides_packages": [ "axi_pkg", "axi_test" ], "top_ports": { "axi_chan_logger": [ { "direction": "in", "name": "addr", "type": "wire", "width": "[AW-1:0]" }, { "direction": "in", "name": "prot_t", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "[DW-1:0]" }, { "direction": "in", "name": "strb", "type": "wire", "width": "[DW/8-1:0]" }, { "direction": "in", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "in", "name": "ax_beat_t", "type": "wire", "width": "" }, { "direction": "in", "name": "w_beat_t", "type": "wire", "width": "" }, { "direction": "in", "name": "b_beat_t", "type": "wire", "width": "" }, { "direction": "in", "name": "r_beat_t", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_type_t", "type": "wire", "width": "" }, { "direction": "in", "name": "int", "type": "wire", "width": "" }, { "direction": "in", "name": "user_rand", "type": "wire", "width": "" }, { "direction": "in", "name": "function", "type": "wire", "width": "" }, { "direction": "in", "name": "is_read", "type": "wire", "width": "" }, { "direction": "in", "name": "user_t", "type": "wire", "width": "" }, { "direction": "in", "name": "bit", "type": "wire", "width": "" }, { "direction": "in", "name": "task", "type": "wire", "width": "" }, { "direction": "in", "name": "string", "type": "wire", "width": "" }, { "direction": "in", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "strb_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_id_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "byte_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "end_sim_i", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "w_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "w_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "b_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "b_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "ar_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ar_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "r_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "r_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "r_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_cut", "latest": "master", "versions": [ "master" ], "description": "Decouples AXI master and slave ports with optional register stages on individual channels.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cut" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_cut_intf", "latest": "master", "versions": [ "master" ], "description": "Cuts AXI transaction paths with optional register stages to decouple master and slave timing domains.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cut", "interface", "intf" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_cut_intf": [ { "direction": "in", "name": "and", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_delayer", "latest": "master", "versions": [ "master" ], "description": "Delays AXI transactions on request and response paths with configurable fixed or random latency.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "delayer" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_delayer": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_delayer_intf", "latest": "master", "versions": [ "master" ], "description": "Introduces configurable fixed or random delays on AXI request and response channels between slave and master ports.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "delayer", "interface", "intf" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_delayer_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_demux", "latest": "master", "versions": [ "master" ], "description": "Demultiplexes a single AXI slave port to multiple AXI master ports based on address-based selection signals.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": 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"library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "converter", "dw" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "provides_packages": [ "axi_pkg" ], "top_ports": { "axi_dw_converter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_mst_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_dw_converter_intf", "latest": "master", "versions": [ "master" ], "description": "Converts AXI transactions between different data widths on slave and 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"master" ], "description": "Converts AXI transactions from wider slave port to narrower master port data width.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "downsizer", "dw" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "provides_packages": [ "axi_pkg" ] }, { "namespace": "pulp-platform", "name": "axi_dw_upsizer", "latest": "master", "versions": [ "master" ], "description": "Converts AXI transactions from a narrower slave port to a wider master port.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "dw", "upsizer" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "provides_packages": [ "axi_pkg" ] }, { "namespace": "pulp-platform", "name": "axi_err_slv", "latest": "master", "versions": [ "master" ], "description": "AXI error slave that responds to all transactions with configurable error codes and data.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "err", "slv" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_fifo", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "buffer", "bus", "fifo", "queue" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_fifo": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_fifo_delay_dyn", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "buffer", "bus", "delay", "dyn", "fifo", "queue" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_fifo_delay_dyn": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "w_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "b_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "ar_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "r_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "delay_i", "type": "wire", "width": "[CounterWidth-1:0]" }, { "direction": "in", "name": "payload_t", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "delay", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_fifo_delay_dyn_intf", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "buffer", "bus", "delay", "dyn", "fifo", "interface", "intf", "queue" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_fifo_delay_dyn_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "w_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "b_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "ar_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "r_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "delay_i", "type": "wire", "width": "[CounterWidth-1:0]" }, { "direction": "in", "name": "payload_t", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "delay", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_fifo_intf", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "buffer", "bus", "fifo", "interface", "intf", "queue" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_fifo_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_from_mem", "latest": "master", "versions": [ "master" ], "description": "ROM with memory interface", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "mem" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_from_mem": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_req_i", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_addr_i", "type": "wire", "width": "[MemAddrWidth-1:0]" }, { "direction": "in", "name": "mem_we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_wdata_i", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "in", "name": "mem_be_i", "type": "wire", "width": "[DataWidth/8-1:0]" }, { "direction": "out", "name": "mem_gnt_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_rsp_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_rsp_rdata_o", "type": "wire", "width": "[DataWidth-1:0]" }, { "direction": "out", "name": "mem_rsp_error_o", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_rsp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_id_remap", "latest": "master", "versions": [ "master" ], "description": "Remaps AXI transaction IDs from a wider slave port to a narrower master port while enforcing per-ID and total in-flight transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "id", "remap" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_id_remap_intf", "latest": "master", "versions": [ "master" ], "description": "Remaps AXI transaction IDs from a wider slave port to a narrower master port while enforcing per-ID and total in-flight transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "id", "interface", "intf", "remap" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_id_remap_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "and", "type": "wire", "width": "" }, { "direction": "out", "name": "IDs", "type": "wire", "width": "" }, { "direction": "in", "name": "ID", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "field_t", "type": "wire", "width": "" }, { "direction": "out", "name": "idx_t", "type": "wire", "width": "" }, { "direction": "out", "name": "full_o", "type": "wire", "width": "" }, { "direction": "in", "name": "push_i", "type": "wire", "width": "" }, { "direction": "in", "name": "id_inp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "exists_o", "type": "wire", "width": "" }, { "direction": "out", "name": "exists_full_o", "type": "wire", "width": "" }, { "direction": "in", "name": "pop_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_id_remap_table", "latest": "master", "versions": [ "master" ], "description": "Remaps AXI transaction IDs from a wide slave port to a narrower master port while enforcing in-flight transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "id", "remap", "table" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_id_remap_table": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "and", "type": "wire", "width": "" }, { "direction": "out", "name": "IDs", "type": "wire", "width": "" }, { "direction": "in", "name": "ID", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "field_t", "type": "wire", "width": "" }, { "direction": "out", "name": "idx_t", "type": "wire", "width": "" }, { "direction": "out", "name": "full_o", "type": "wire", "width": "" }, { "direction": "in", "name": "push_i", "type": "wire", "width": "" }, { "direction": "in", "name": "id_inp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "exists_o", "type": "wire", "width": "" }, { "direction": "out", "name": "exists_full_o", "type": "wire", "width": "" }, { "direction": "in", "name": "pop_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_id_serialize", "latest": "master", "versions": [ "master" ], "description": "Serializes AXI transactions by remapping slave port IDs to master port IDs while enforcing per-ID transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "id", "serialize" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_id_serialize_intf", "latest": "master", "versions": [ "master" ], "description": "Remaps AXI transaction IDs from a wide slave port to a narrower master port with configurable ID mapping and transaction tracking.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "id", "interface", "intf", "serialize" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_id_serialize_intf": [ { "direction": "in", "name": "IDs", "type": "wire", "width": "" }, { "direction": "out", "name": "ID", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "with", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_interleaved_xbar", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interleaved", "xbar" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_interleaved_xbar": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "in", "name": "interleaved_mode_ena_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_default_mst_port_i", "type": "wire", "width": "[Cfg.NoSlvPorts-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_interleaved_xbar_intf", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "interleaved", "intf", "xbar" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_interleaved_xbar_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "in", "name": "interleaved_mode_ena_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_default_mst_port_i", "type": "wire", "width": "[Cfg.NoSlvPorts-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_inval_filter", "latest": "master", "versions": [ "master" ], "description": "Description: Listens to AXI4 AW channel and issue single cacheline invalidations. All other channels are passed through.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "filter", "inval" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "header", "top_ports": { "axi_inval_filter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "inval_addr_o", "type": "wire", "width": "[AddrWidth-1:0]" }, { "direction": "out", "name": "inval_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "inval_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_isolate", "latest": "master", "versions": [ "master" ], "description": "Isolates an AXI master port from a slave port by blocking transactions and optionally returning error responses.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "isolate" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_isolate": [ { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "isolate_i", "type": "wire", "width": "" }, { "direction": "out", "name": "isolated_o", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_isolate_inner", "latest": "master", "versions": [ "master" ], "description": "Isolates AXI slave port from master port, blocking transactions and optionally returning error responses when isolation is active.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "inner", "isolate" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_isolate_inner": [ { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "isolate_i", "type": "wire", "width": "" }, { "direction": "out", "name": "isolated_o", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_isolate_intf", "latest": "master", "versions": [ "master" ], "description": "Isolates an AXI master port from slave port requests, optionally terminating transactions with error responses.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "isolate" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_isolate_intf": [ { "direction": "out", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "isolate_i", "type": "wire", "width": "" }, { "direction": "out", "name": "isolated_o", "type": "wire", "width": "" }, { "direction": "out", "name": "signal", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_iw_converter", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4+ATOP transactions between slave and master ports with different ID widths.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "converter", "iw" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_iw_converter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_iw_converter_intf", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4+ATOP transactions between slave and master ports with different ID widths and transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "converter", "interface", "intf", "iw" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_iw_converter_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "slv_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_join_intf", "latest": "master", "versions": [ "master" ], "description": "Joins/passes through an AXI slave interface to an AXI master interface.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "join" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_join_intf": [ { "direction": "Slave", "name": "in", "type": "AXI_BUS.Slave", "width": "" }, { "direction": "Master", "name": "out", "type": "AXI_BUS.Master", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lfsr", "latest": "master", "versions": [ "master" ], "description": "AXI4 interface with dual LFSR shift registers for serial write/read data manipulation and testmode support.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "feedback", "lfsr", "linear", "prng", "register", "shift" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lfsr": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_rsp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "w_ser_data_i", "type": "wire", "width": "" }, { "direction": "out", "name": "w_ser_data_o", "type": "wire", "width": "" }, { "direction": "in", "name": "w_ser_en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "r_ser_data_i", "type": "wire", "width": "" }, { "direction": "out", "name": "r_ser_data_o", "type": "wire", "width": "" }, { "direction": "in", "name": "r_ser_en_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_cdc_dst_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "dst", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_cdc_dst_intf": [ { "direction": "in", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_aw_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_aw_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_w_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_w_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_slave_b_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_slave_b_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_slave_ar_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_slave_ar_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "r_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_slave_r_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_slave_r_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_cdc_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_cdc_intf": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_cdc_src_intf", "latest": "master", "versions": [ "master" ], "description": "Clock domain crossing", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cdc", "clock", "crossing", "domain", "interface", "intf", "lightweight", "lite", "src" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_cdc_src_intf": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "aw_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_aw_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_aw_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "w_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_w_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_w_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "b_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_master_b_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_master_b_rptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "ar_chan_t", "type": "wire", "width": "" }, { "direction": "out", "name": "async_data_master_ar_wptr_o", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "async_data_master_ar_rptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "in", "name": "r_chan_t", "type": "wire", "width": "" }, { "direction": "in", "name": "async_data_master_r_wptr_i", "type": "wire", "width": "[LogDepth:0]" }, { "direction": "out", "name": "async_data_master_r_rptr_o", "type": "wire", "width": "[LogDepth:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_cut_intf", "latest": "master", "versions": [ "master" ], "description": "AXI cut module that optionally registers request/response signals to break combinational paths between slave and master ports.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "cut", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_cut_intf": [ { "direction": "in", "name": "and", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_demux", "latest": "master", "versions": [ "master" ], "description": "Demultiplexes a single AXI4-Lite slave port to multiple master ports based on address write/read select signals.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "demultiplexer", "demux", "lightweight", "lite" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_lite_demux_intf", "latest": "master", "versions": [ "master" ], "description": "Demultiplexes a single AXI4-Lite slave port to multiple master ports based on address-phase select signals.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "demultiplexer", "demux", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_demux_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "select_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "control", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_dw_converter", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4-Lite transactions between different data widths on slave and master ports.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "converter", "dw", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_dw_converter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_slv_res_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_mst_res_t", "type": "wire", "width": "" }, { "direction": "out", "name": "address", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "sel_t", "type": "wire", "width": "" }, { "direction": "in", "name": "spill", "type": "wire", "width": "" }, { "direction": "out", "name": "assignment", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_dw_converter_intf", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4-Lite transactions between slave and master ports with different data widths.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "converter", "dw", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_dw_converter_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_slv_res_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_mst_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_mst_res_t", "type": "wire", "width": "" }, { "direction": "out", "name": "address", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "sel_t", "type": "wire", "width": "" }, { "direction": "in", "name": "spill", "type": "wire", "width": "" }, { "direction": "out", "name": "assignment", "type": "wire", "width": "" }, { "direction": "out", "name": "is", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_join_intf", "latest": "master", "versions": [ "master" ], "description": "Passes through AXI-Lite transactions from slave input to master output interface.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "join", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_join_intf": [ { "direction": "Slave", "name": "in", "type": "AXI_LITE.Slave", "width": "" }, { "direction": "Master", "name": "out", "type": "AXI_LITE.Master", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_mailbox", "latest": "master", "versions": [ "master" ], "description": "Command mailbox with FIFO interface and interrupt support", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite", "mailbox" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_mailbox": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "irq_o", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_w_full_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_push_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_flush_o", "type": "wire", "width": "" }, { "direction": "in", "name": "usage_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_r_empty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_pop_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_flush_o", "type": "wire", "width": "" }, { "direction": "out", "name": "clear_irq_o", "type": "wire", "width": "" }, { "direction": "out", "name": "type", "type": "wire", "width": "" }, { "direction": "out", "name": "spill", "type": "wire", "width": "" }, { "direction": "out", "name": "depending", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_mailbox_intf", "latest": "master", "versions": [ "master" ], "description": "Command mailbox with FIFO interface and interrupt support", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite", "mailbox" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_mailbox_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "irq_o", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_w_full_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_push_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_flush_o", "type": "wire", "width": "" }, { "direction": "in", "name": "usage_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_r_empty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_pop_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_flush_o", "type": "wire", "width": "" }, { "direction": "out", "name": "clear_irq_o", "type": "wire", "width": "" }, { "direction": "out", "name": "type", "type": "wire", "width": "" }, { "direction": "out", "name": "spill", "type": "wire", "width": "" }, { "direction": "out", "name": "depending", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_mailbox_slave", "latest": "master", "versions": [ "master" ], "description": "Slave with FIFO interface and interrupt support", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite", "mailbox", "slave" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_mailbox_slave": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "irq_o", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "for", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_w_full_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_push_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_w_flush_o", "type": "wire", "width": "" }, { "direction": "in", "name": "usage_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mbox_r_empty_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_pop_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mbox_r_flush_o", "type": "wire", "width": "" }, { "direction": "out", "name": "clear_irq_o", "type": "wire", "width": "" }, { "direction": "out", "name": "type", "type": "wire", "width": "" }, { "direction": "out", "name": "spill", "type": "wire", "width": "" }, { "direction": "out", "name": "depending", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_multicut_intf", "latest": "master", "versions": [ "master" ], "description": "Inserts multiple pipeline stages on AXI bus to break combinational paths and improve timing.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite", "multicut" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_lite_mux", "latest": "master", "versions": [ "master" ], "description": "Multiplexes multiple AXI4-Lite master ports onto a single slave port with configurable transaction buffering and pipeline stages.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite", "multiplexer", "mux" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_lite_mux_intf", "latest": "master", "versions": [ "master" ], "description": "Multiplexes multiple AXI4-Lite master ports onto a single slave port with configurable transaction buffering and pipeline stages.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite", "multiplexer", "mux" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_mux_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_regs", "latest": "master", "versions": [ "master" ], "description": "AXI4-Lite slave interface that manages a register file with configurable access protection and byte-level read-only enforcement.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_regs": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_active_o", "type": "wire", "width": "[RegNumBytes-1:0]" }, { "direction": "out", "name": "rd_active_o", "type": "wire", "width": "[RegNumBytes-1:0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "" }, { "direction": "in", "name": "byte_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "reg_load_i", "type": "wire", "width": "[RegNumBytes-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_regs_intf", "latest": "master", "versions": [ "master" ], "description": "AXI4-Lite slave module that manages memory-mapped registers with configurable read-only bytes and access protection.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_regs_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "wr_active_o", "type": "wire", "width": "[RegNumBytes-1:0]" }, { "direction": "out", "name": "rd_active_o", "type": "wire", "width": "[RegNumBytes-1:0]" }, { "direction": "in", "name": "value", "type": "wire", "width": "" }, { "direction": "in", "name": "byte_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "reg_load_i", "type": "wire", "width": "[RegNumBytes-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_to_apb", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4-Lite protocol requests to APB4 protocol for routing to multiple slave devices based on address mapping.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "advanced", "amba", "apb", "axi", "bus", "lightweight", "lite", "peripheral" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_to_apb": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "apb_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "apb_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "out", "name": "apb_req_o", "type": "wire", "width": "" }, { "direction": "out", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "pprot_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "sel_t", "type": "wire", "width": "" }, { "direction": "out", "name": "penable_o", "type": "wire", "width": "" }, { "direction": "out", "name": "pwrite_o", "type": "wire", "width": "" }, { "direction": "out", "name": "data_t", "type": "wire", "width": "" }, { "direction": "out", "name": "strb_t", "type": "wire", "width": "" }, { "direction": "in", "name": "pready_i", "type": "wire", "width": "[NoApbSlaves-1:0]" }, { "direction": "in", "name": "pslverr_i", "type": "wire", "width": "[NoApbSlaves-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_to_apb_intf", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4-Lite requests to APB4 transactions with configurable address mapping across multiple slaves.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "advanced", "amba", "apb", "axi", "bus", "interface", "intf", "lightweight", "lite", "peripheral" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_to_apb_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "apb_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "apb_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "out", "name": "apb_req_o", "type": "wire", "width": "" }, { "direction": "out", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "pprot_o", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "sel_t", "type": "wire", "width": "" }, { "direction": "out", "name": "penable_o", "type": "wire", "width": "" }, { "direction": "out", "name": "pwrite_o", "type": "wire", "width": "" }, { "direction": "out", "name": "data_t", "type": "wire", "width": "" }, { "direction": "out", "name": "strb_t", "type": "wire", "width": "" }, { "direction": "in", "name": "pready_i", "type": "wire", "width": "[NoApbSlaves-1:0]" }, { "direction": "in", "name": "pslverr_i", "type": "wire", "width": "[NoApbSlaves-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_to_axi", "latest": "master", "versions": [ "master" ], "description": "Converts AXI-Lite protocol requests to full AXI protocol with configurable data width and cache policies.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_lite_to_axi_intf", "latest": "master", "versions": [ "master" ], "description": "Converts AXI-Lite protocol requests to full AXI protocol with configurable data width and cache policies.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_lite_to_axi_intf": [ { "direction": "in", "name": "req_lite_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_lite_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_xbar", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "lightweight", "lite", "xbar" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_xbar": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "in", "name": "en_default_mst_port_i", "type": "wire", "width": "[Cfg.NoSlvPorts-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_lite_xbar_intf", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "lightweight", "lite", "xbar" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "axi_lite_xbar_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "test_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "in", "name": "en_default_mst_port_i", "type": "wire", "width": "[Cfg.NoSlvPorts-1:0]" }, { "direction": "in", "name": "logic", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_modify_address", "latest": "master", "versions": [ "master" ], "description": "Transforms AXI slave requests by modifying addresses before forwarding to the master port.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "address", "amba", "axi", "bus", "modify" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_modify_address": [ { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_modify_address_intf", "latest": "master", "versions": [ "master" ], "description": "Transforms AXI slave request addresses and forwards them to master port with modified addressing.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "address", "amba", "axi", "bus", "interface", "intf", "modify" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_modify_address_intf": [ { "direction": "in", "name": "slv_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mst_addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mst_req_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_multicut", "latest": "master", "versions": [ "master" ], "description": "Inserts multiple pipeline stages on AXI write/read channels to break timing paths.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "multicut" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_multicut": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_multicut_intf", "latest": "master", "versions": [ "master" ], "description": "Buffers AXI transactions through multiple pipeline stages to break combinational paths between slave and master ports.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "multicut" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_multicut_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "out", "name": "assign", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_mux", "latest": "master", "versions": [ "master" ], "description": "Multiplexes multiple AXI slave ports onto a single AXI master port with configurable transaction buffering and pipeline stages.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "multiplexer", "mux" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_mux_intf", "latest": "master", "versions": [ "master" ], "description": "Multiplexes multiple AXI slave ports onto a single AXI master port with configurable transaction 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"master", "versions": [ "master" ], "description": "AXI4-Lite interface to dual LFSR with independent serial shift ports for read and write path testing.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "feedback", "lfsr", "linear", "opt", "prng", "register", "shift" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_opt_lfsr": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_lite_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_lite_rsp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "w_ser_data_i", "type": "wire", "width": "" }, { "direction": "out", "name": "w_ser_data_o", "type": "wire", "width": "" }, { "direction": "in", "name": "w_ser_en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "r_ser_data_i", "type": "wire", "width": "" }, { "direction": "out", "name": "r_ser_data_o", "type": "wire", "width": "" }, { "direction": "in", "name": "r_ser_en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ser_data_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ser_data_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ser_en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[Width-1:0]" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[Width-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "axi_rw_join", "latest": "master", "versions": [ "master" ], "description": "Multiplexes separate AXI read and write slave ports onto a single AXI master port.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "join", "rw" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_rw_join": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_rw_split", "latest": "master", "versions": [ "master" ], "description": "Splits a single AXI slave port into separate read and write master ports.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "rw", "split" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_rw_split": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_serializer", "latest": "master", "versions": [ "master" ], "description": "Serializes concurrent AXI read and write transactions from slave to master port with configurable transaction limits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "serializer" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "axi_serializer_intf", "latest": "master", "versions": [ "master" ], "description": "Serializes concurrent AXI transactions into sequential requests while tracking in-flight read and write transactions.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "interface", "intf", "serializer" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_serializer_intf": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_slave_compare", "latest": "master", "versions": [ "master" ], "description": "Compares AXI4+ATOP transactions between reference and test channels, flagging mismatches on write/read address, write data, and response phases.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "compare", "slave" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "axi_slave_compare": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_rsp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "id_t", "type": "wire", "width": "" }, { "direction": "out", "name": "w_mismatch_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mismatch_o", "type": "wire", "width": "" }, { "direction": "out", "name": "busy_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "axi_throttle", "latest": "master", "versions": [ "master" ], "description": "Throttles AXI transactions by limiting concurrent write and read requests based on available credits.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "amba", "axi", "bus", "throttle" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": 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Clear Signaling Synchronization", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "cdc", "clock", "crossing", "ctrlr", "domain", "reset" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "header", "provides_packages": [ "cdc_reset_ctrlr_pkg" ] }, { "namespace": "pulp-platform", "name": "cdc_reset_ctrlr_half", "latest": "master", "versions": [ "master" ], "description": "Title : CDC Clear Signaling Synchronization", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "cdc", "clock", "crossing", "ctrlr", "domain", "half", "reset" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "header", "provides_packages": [ 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"direction": "out", "name": "clk_o", "type": "wire", "width": "" }, { "direction": "out", "name": "during", "type": "wire", "width": "" }, { "direction": "in", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "we", "type": "wire", "width": "" }, { "direction": "out", "name": "and", "type": "wire", "width": "" }, { "direction": "out", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "stages", "type": "wire", "width": "" }, { "direction": "out", "name": "gate", "type": "wire", "width": "" }, { "direction": "out", "name": "back", "type": "wire", "width": "" }, { "direction": "in", "name": "before", "type": "wire", "width": "" }, { "direction": "out", "name": "OR", "type": "wire", "width": "" }, { "direction": "in", "name": "but", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "clock_divider", "latest": "master", "versions": [ "master" ], "description": "Divides input clock frequency by a programmable factor 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[], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "generic_LFSR_8bit": [ { "direction": "out", "name": "data_OH_o", "type": "wire", "width": "[OH_WIDTH-1:0]" }, { "direction": "out", "name": "data_BIN_o", "type": "wire", "width": "[BIN_WIDTH-1:0]" }, { "direction": "in", "name": "enable_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "generic_fifo", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "buffer", "fifo", "queue" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "generic_fifo": [ { "direction": "in", "name": "clk", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_n", "type": "wire", "width": "" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "grant_o", "type": "wire", "width": "" }, { "direction": "out", "name": "data_o", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "grant_i", "type": "wire", "width": "" }, { "direction": "in", "name": "test_mode_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "generic_fifo_adv", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ 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"hash_block", "latest": "master", "versions": [ "master" ], "description": "Counting Bloom filter that performs parallel hash-based lookups, increments, and decrements on fixed-width counter buckets.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "block", "hash" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "hash_block": [ { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "look_data_i", "type": "wire", "width": "[InpWidth-1:0]" }, { "direction": "out", "name": "look_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "incr_data_i", "type": "wire", "width": "[InpWidth-1:0]" }, { "direction": "in", "name": "incr_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "decr_data_i", "type": "wire", "width": "[InpWidth-1:0]" }, { "direction": "in", "name": "decr_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "filter_clear_i", "type": "wire", "width": "" }, { "direction": "out", "name": "filter_usage_o", "type": "wire", "width": "[HashWidth-1:0]" }, { "direction": "out", "name": "filter_full_o", "type": "wire", "width": "" }, { "direction": "out", "name": "filter_empty_o", "type": "wire", "width": "" }, { "direction": "out", "name": "filter_error_o", "type": "wire", "width": "" }, { "direction": "out", "name": "Flags", "type": "wire", "width": "" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[InpWidth-1:0]" }, { "direction": "out", "name": "indicator_o", "type": "wire", "width": "[2**HashWidth-1:0]" }, { "direction": "out", "name": "assignment", "type": "wire", "width": "" } ] } }, { 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"direction": "in", "name": "inp_req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "inp_gnt_o", "type": "wire", "width": "" }, { "direction": "in", "name": "exists_req_i", "type": "wire", "width": "[NUM_CMP_PORTS-1:0]" }, { "direction": "out", "name": "exists_o", "type": "wire", "width": "[NUM_CMP_PORTS-1:0]" }, { "direction": "out", "name": "exists_gnt_o", "type": "wire", "width": "[NUM_CMP_PORTS-1:0]" }, { "direction": "in", "name": "oup_pop_i", "type": "wire", "width": "" }, { "direction": "in", "name": "oup_req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "oup_data_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "oup_gnt_o", "type": "wire", "width": "" }, { "direction": "out", "name": "full_o", "type": "wire", "width": "" }, { "direction": "out", "name": "empty_o", "type": "wire", "width": "" }, { "direction": "out", "name": "request", "type": "wire", "width": "" }, { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "id", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "isochronous_4phase_handshake", "latest": "master", "versions": [ "master" ], "description": "Synchronizes ready/valid handshake signals between two independent clock domains using 4-phase protocol.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "4phase", "handshake", "isochronous" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "isochronous_4phase_handshake": [ { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "src_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "src_ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" }, { "direction": "out", "name": "dst_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "isochronous_spill_register", "latest": "master", "versions": [ "master" ], "description": "Synchronizes data across clock domains using isochronous handshake with optional bypass mode.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "isochronous", "register", "spill" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "isochronous_spill_register": [ { "direction": "in", "name": "and", "type": "wire", "width": "" }, { "direction": "out", "name": "in", "type": "wire", "width": "" }, { "direction": "in", "name": "src_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "src_rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "src_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "src_ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "T", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_rst_ni", "type": "wire", "width": "" }, { "direction": "out", "name": "dst_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "dst_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "lfsr_8bit", "latest": "master", "versions": [ "master" ], "description": "Generates pseudo-random 8-bit values for cache way selection using a linear feedback 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"" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "clear_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clear_max_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "load_i", "type": "wire", "width": "" }, { "direction": "in", "name": "down_i", "type": "wire", "width": "" }, { "direction": "in", "name": "delta_i", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "in", "name": "d_i", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "q_o", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "max_o", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "overflow_o", "type": "wire", "width": "" }, { "direction": "out", "name": "overflow_max_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "mem_stream_to_banks_detailed", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4+ATOP transactions into parallel memory bank requests with configurable width distribution and response buffering.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "banks", "detailed", "mem", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "preserved", "top_ports": { "mem_stream_to_banks_detailed": [ { "direction": "out", "name": "fifo", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "out", "name": "busy_o", "type": "wire", "width": "" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_req_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "mem_gnt_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "out", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_data_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_strb_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_pkg", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_lock_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "out", "name": "mem_we_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "out", "name": "mem_id_t", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_user_t", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_rvalid_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "mem_err_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "mem_exokay_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "address", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "write", "type": "wire", "width": "" }, { "direction": "in", "name": "response", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "gnt_o", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_strb_t", "type": "wire", "width": "" }, { "direction": "in", "name": "wuser_t", "type": "wire", "width": "" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "out", "name": "rvalid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "rready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "inp_ruser_t", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_req_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "bank_gnt_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "out", "name": "oup_data_t", "type": "wire", "width": "" }, { "direction": "out", "name": "oup_strb_t", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_we_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "bank_rvalid_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "oup_ruser_t", "type": "wire", "width": "" }, { "direction": "out", "name": "if", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "mem_to_banks", "latest": "master", "versions": [ "master" ], "description": "Splits memory transactions across multiple banks, distributing data and address bits while managing request/response flow.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "banks", "mem" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "mem_to_banks": [ { "direction": "in", "name": "address", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "write", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "" }, { "direction": "out", "name": "gnt_o", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_strb_t", "type": "wire", "width": "" }, { "direction": "in", "name": "atop_t", "type": "wire", "width": "" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "out", "name": "rvalid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_req_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "bank_gnt_i", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "out", "name": "oup_data_t", "type": "wire", "width": "" }, { "direction": "out", "name": "oup_strb_t", "type": "wire", "width": "" }, { "direction": "out", "name": "bank_we_o", "type": "wire", "width": "[NumBanks-1:0]" }, { "direction": "in", "name": "bank_rvalid_i", "type": "wire", "width": "[NumBanks-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "mem_to_banks_detailed", "latest": "master", "versions": [ "master" ], "description": "Splits memory transactions across multiple banks, distributing data and strobe signals while managing address translation and response aggregation.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "banks", "detailed", "mem" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "multiaddr_decode", "latest": "master", "versions": [ "master" ], "description": "Decodes which address map rules match a given address set in {addr, mask} representation.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "decode", "multiaddr" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "multiaddr_decode": [ { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rule_t", "type": "wire", "width": "" }, { "direction": "out", "name": "select_o", "type": "wire", "width": "[NoIndices-1:0]" }, { "direction": "out", "name": "dec_valid_o", "type": "wire", "width": "" }, { "direction": "out", "name": "dec_error_o", "type": "wire", "width": "" }, { "direction": "in", "name": "address", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "mv_filter", "latest": "master", "versions": [ "master" ], "description": "Median voting filter that outputs the majority bit value from recent samples with configurable threshold.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "filter", "mv" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "mv_filter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "sample_i", "type": "wire", "width": "" }, { "direction": "in", "name": "clear_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "passthrough_stream_fifo", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "buffer", "fifo", "passthrough", "queue", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "passthrough_stream_fifo": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "type_t", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "plru_tree", "latest": "master", "versions": [ "master" ], "description": "Implements a pseudo-least-recently-used (PLRU) replacement policy tracker that identifies the least recently used cache entry among multiple entries.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "plru", "tree" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "plru_tree": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "used_i", "type": "wire", "width": "[ENTRIES-1:0]" }, { "direction": "out", "name": "plru_o", "type": "wire", "width": "[ENTRIES-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "popcount", "latest": "master", "versions": [ "master" ], "description": "Counts the number of set bits in a fixed-width input data word.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "popcount": [ { "direction": "in", "name": "vector", "type": "wire", "width": "" }, { "direction": "out", "name": "result", "type": "wire", "width": "" }, { "direction": "in", "name": "data_i", "type": "wire", "width": "[ INPUT_WIDTH-1:0]" }, { "direction": "out", "name": "popcount_o", "type": "wire", "width": "[PopcountWidth-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "prioarbiter", "latest": "master", "versions": [ "master" ], "description": "Arbitrates multiple requests using priority encoding, outputting the highest-priority granted request index and validity signal.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "prioarbiter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "[NUM_REQ-1:0]" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "[NUM_REQ-1:0]" }, { "direction": "out", "name": "vld_o", "type": "wire", "width": "" }, { "direction": "out", "name": "idx_o", "type": "wire", "width": "[$clog2(NUM_REQ)-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "pulp_sync_wedge", "latest": "master", "versions": [ "master" ], "description": "Synchronizes an asynchronous serial input across clock domains and detects rising and falling edges.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "pulp", "sync", "synchronizer", "synchronous", "wedge" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "read", "latest": "master", "versions": [ "master" ], "description": "Date: 07.11.2022 Description: Dummy circuit to assign a signal, prevent signal being removed after non-ungroupped synthesis compilation", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "header", "top_ports": { "read": [ { "direction": "in", "name": "T", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "ring_buffer", "latest": "master", "versions": [ "master" ], "description": "This module implements a flexible ring buffer with decoupled write and read access. It supports sequential writes and random reads with a valid/ready handshake protocol.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "buffer", "ring" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "header", "top_ports": { "ring_buffer": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "wvalid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "wready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "data_t", "type": "wire", "width": "" }, { "direction": "in", "name": "rvalid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "rready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_t", "type": "wire", "width": "" }, { "direction": "in", "name": "advance_i", "type": "wire", "width": "" }, { "direction": "in", "name": "step_t", "type": "wire", "width": "" }, { "direction": "out", "name": "full_o", "type": "wire", "width": "" }, { "direction": "out", "name": "empty_o", "type": "wire", "width": "" }, { "direction": "out", "name": "logic", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "rr_arb_tree", "latest": "master", "versions": [ "master" ], "description": "Round-robin tree arbiter that selects among NumIn requests and multiplexes corresponding data with fair or simple priority rotation.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "arb", "arbiter", "arbitration", "rr", "tree" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "rrarbiter", "latest": "master", "versions": [ "master" ], "description": "Round-robin arbiter that prioritizes and grants access to one of multiple concurrent requests.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "rrarbiter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "[NUM_REQ-1:0]" }, { "direction": "out", "name": "ack_o", "type": "wire", "width": "[NUM_REQ-1:0]" }, { "direction": "out", "name": "vld_o", "type": "wire", "width": "" }, { "direction": "out", "name": "idx_o", "type": "wire", "width": "[$clog2(NUM_REQ)-1:0]" } ] } }, { "namespace": "pulp-platform", "name": "rstgen", "latest": "master", "versions": [ "master" ], "description": "Generates synchronized reset signals with optional test mode override and initialization output.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "serial_deglitch", "latest": "master", "versions": [ "master" ], "description": "Filters noisy serial input data through a shift register to eliminate glitches.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "deglitch", "serial" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "serial_deglitch": [ { "direction": "out", "name": "high", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "d_i", "type": "wire", "width": "" }, { "direction": "out", "name": "q_o", "type": "wire", "width": "" }, { "direction": "out", "name": "process", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "shift_reg", "latest": "master", "versions": [ "master" ], "description": "Shift register that delays an input signal by a configurable number of stages.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "reg", "register", "shift" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "shift_reg": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "dtype", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "spill_register", "latest": "master", "versions": [ "master" ], "description": "Buffers data with ready/valid handshake, decoupling upstream and downstream timing.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "register", "spill" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "sram", "latest": "master", "versions": [ "master" ], "description": "RAM with memory interface", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "sram": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "req_i", "type": "wire", "width": "" }, { "direction": "in", "name": "we_i", "type": "wire", "width": "" }, { "direction": "in", "name": "addr_i", "type": "wire", "width": "[$clog2(NUM_WORDS)-1:0]" }, { "direction": "in", "name": "wdata_i", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "in", "name": "be_i", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "rdata_o", "type": "wire", "width": "[DATA_WIDTH-1:0]" }, { "direction": "out", "name": "when", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_arbiter", "latest": "master", "versions": [ "master" ], "description": "Arbiter with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "arbiter", "arbitration", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "stream_arbiter": [ { "direction": "in", "name": "streams", "type": "wire", "width": "" }, { "direction": "out", "name": "stream", "type": "wire", "width": "" }, { "direction": "out", "name": "handshake", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "DATA_T", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_valid_i", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "out", "name": "inp_ready_o", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "out", "name": "oup_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "oup_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_arbiter_flushable", "latest": "master", "versions": [ "master" ], "description": "Arbiter with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "arbiter", "arbitration", "flushable", "stream" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports" }, { "namespace": "pulp-platform", "name": "stream_delay", "latest": "master", "versions": [ "master" ], "description": "Delays a ready/valid stream by a fixed or random number of cycles while maintaining handshake protocol.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "delay", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_delay": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "payload_t", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_fifo", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "buffer", "fifo", "queue", "stream" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports" }, { "namespace": "pulp-platform", "name": "stream_fifo_delay_dyn", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/axi.git", "tags": [ "buffer", "delay", "dyn", "fifo", "queue", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-05-07T16:14:15+02:00", "desc_source": "ports", "top_ports": { "stream_fifo_delay_dyn": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "aw_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "w_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "b_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "ar_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "r_delay_i", "type": "wire", "width": "[DelayWidth-1:0]" }, { "direction": "in", "name": "axi_req_t", "type": "wire", "width": "" }, { "direction": "out", "name": "axi_resp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "delay_i", "type": "wire", "width": "[CounterWidth-1:0]" }, { "direction": "in", "name": "payload_t", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "delay", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_fifo_optimal_wrap", "latest": "master", "versions": [ "master" ], "description": "FIFO buffer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "buffer", "fifo", "optimal", "queue", "stream", "wrap" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "stream_fifo_optimal_wrap": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "out", "name": "usage_o", "type": "wire", "width": "[AddrDepth-1:0]" }, { "direction": "in", "name": "interface", "type": "wire", "width": "" }, { "direction": "in", "name": "type_t", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_filter", "latest": "master", "versions": [ "master" ], "description": "Filter with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "filter", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "stream_filter": [ { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "drop_i", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_fork_dynamic", "latest": "master", "versions": [ "master" ], "description": "Dynamically routes an input stream to multiple output streams based on a selection mask.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "dynamic", "fork", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_fork_dynamic": [ { "direction": "in", "name": "stream", "type": "wire", "width": "" }, { "direction": "out", "name": "streams", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "handshake", "type": "wire", "width": "" }, { "direction": "in", "name": "sel_i", "type": "wire", "width": "[N_OUP-1:0]" }, { "direction": "in", "name": "sel_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "sel_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "[N_OUP-1:0]" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "[N_OUP-1:0]" }, { "direction": "out", "name": "handshaking", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_join", "latest": "master", "versions": [ "master" ], "description": "Combines multiple input streams into a single output stream using ready-valid handshakes.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "join", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_join": [ { "direction": "in", "name": "streams", "type": "wire", "width": "" }, { "direction": "out", "name": "stream", "type": "wire", "width": "" }, { "direction": "out", "name": "handshake", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_valid_i", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "out", "name": "inp_ready_o", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "out", "name": "oup_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "oup_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_mux", "latest": "master", "versions": [ "master" ], "description": "Multiplexer with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "multiplexer", "mux", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports", "top_ports": { "stream_mux": [ { "direction": "out", "name": "to", "type": "wire", "width": "" }, { "direction": "in", "name": "DATA_T", "type": "wire", "width": "" }, { "direction": "in", "name": "inp_valid_i", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "out", "name": "inp_ready_o", "type": "wire", "width": "[N_INP-1:0]" }, { "direction": "in", "name": "inp_sel_i", "type": "wire", "width": "[SEL_WIDTH-1:0]" }, { "direction": "out", "name": "oup_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "oup_ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_omega_net", "latest": "master", "versions": [ "master" ], "description": "Streaming omega network that arbitrates and routes data from multiple inputs to multiple outputs using round-robin arbitration with AXI-style handshaking.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "net", "omega", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_omega_net": [ { "direction": "out", "name": "selection", "type": "wire", "width": "" }, { "direction": "out", "name": "at", "type": "wire", "width": "" }, { "direction": "in", "name": "index", "type": "wire", "width": "" }, { "direction": "in", "name": "the", "type": "wire", "width": "" }, { "direction": "out", "name": "came", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "flush_i", "type": "wire", "width": "" }, { "direction": "in", "name": "idx_inp_t", "type": "wire", "width": "" }, { "direction": "in", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "payload_t", "type": "wire", "width": "" }, { "direction": "out", "name": "port", "type": "wire", "width": "" }, { "direction": "in", "name": "sel_oup_t", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "[NumInp-1:0]" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "[NumInp-1:0]" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "[NumOut-1:0]" }, { "direction": "out", "name": "can", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "[NumOut-1:0]" }, { "direction": "in", "name": "of", "type": "wire", "width": "" }, { "direction": "in", "name": "shuffle", "type": "wire", "width": "" }, { "direction": "in", "name": "ports", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_register", "latest": "master", "versions": [ "master" ], "description": "Buffers streaming data with ready/valid handshaking, decoupling input and output flow control.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "register", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_register": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "clr_i", "type": "wire", "width": "" }, { "direction": "in", "name": "testmode_i", "type": "wire", "width": "" }, { "direction": "in", "name": "port", "type": "wire", "width": "" }, { "direction": "in", "name": "valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "T", "type": "wire", "width": "" }, { "direction": "out", "name": "valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "ready_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_throttle", "latest": "master", "versions": [ "master" ], "description": "Limits outstanding requests by gating request flow based on available credit count using ready/valid handshakes.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "stream", "throttle" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_throttle": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "req_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "req_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "req_ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "req_ready_o", "type": "wire", "width": "" }, { "direction": "in", "name": "rsp_valid_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rsp_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "credit_t", "type": "wire", "width": "" }, { "direction": "in", "name": "is", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_to_mem", "latest": "master", "versions": [ "master" ], "description": "Bridges a memory request/response stream interface with buffering to decouple downstream consumers from memory latency.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "mem", "stream" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "stream_to_mem": [ { "direction": "out", "name": "data", "type": "wire", "width": "" }, { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_req_t", "type": "wire", "width": "" }, { "direction": "in", "name": "req_valid_i", "type": "wire", "width": "" }, { "direction": "out", "name": "req_ready_o", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_resp_t", "type": "wire", "width": "" }, { "direction": "out", "name": "resp_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "resp_ready_i", "type": "wire", "width": "" }, { "direction": "out", "name": "mem_req_valid_o", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_req_ready_i", "type": "wire", "width": "" }, { "direction": "in", "name": "mem_resp_valid_i", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "stream_xbar", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch with ready/valid handshake", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "stream", "xbar" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "ports" }, { "namespace": "pulp-platform", "name": "sync_wedge", "latest": "master", "versions": [ "master" ], "description": "Synchronizes an asynchronous serial input and detects its rising and falling edges.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "sync", "synchronizer", "synchronous", "wedge" ], "role": "component", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved" }, { "namespace": "pulp-platform", "name": "trip_counter", "latest": "master", "versions": [ "master" ], "description": "Counts up by delta_i each cycle until reaching bound_i, signaling completion via trip_o.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [ "counter", "trip" ], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "trip_counter": [ { "direction": "in", "name": "clk_i", "type": "wire", "width": "" }, { "direction": "in", "name": "rst_ni", "type": "wire", "width": "" }, { "direction": "in", "name": "en_i", "type": "wire", "width": "" }, { "direction": "in", "name": "delta_i", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "in", "name": "bound_i", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "q_o", "type": "wire", "width": "[WIDTH-1:0]" }, { "direction": "out", "name": "last_o", "type": "wire", "width": "" }, { "direction": "out", "name": "trip_o", "type": "wire", "width": "" } ] } }, { "namespace": "pulp-platform", "name": "unread", "latest": "master", "versions": [ "master" ], "description": "Marks an input signal as intentionally unused to suppress compiler warnings.", "license": "Apache-2.0", "language": "systemverilog", "library": "work", "source_url": "https://github.com/pulp-platform/common_cells.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-04-15T23:18:14Z", "updated_at": "2026-04-17T14:02:22+00:00", "desc_source": "preserved", "top_ports": { "unread": [ { "direction": "in", "name": "d_i", "type": "wire", "width": "" } ] } }, { "namespace": "routertl-stubs", "name": "wbgenplus", "latest": "6f122afe0685", "versions": [ "6f122afe0685", "HEAD" ], "description": "Empty stub for wbgenplus_pkg. mkreider/wbgenplus's codegen emits `use work.wbgenplus_pkg.all;` in every generated VHDL file unconditionally, but the runtime support package the clause references was never published in any public repo (RTL-P4.35: verified across mkreider/wbgenplus, GSI bel_projects, GSI's wr-cores fork, mkreider/eca, gitlab.com/ohwr/project \u2014 0 hits filename-wide). Audit of consumers in white-rabbit/wr-eca shows zero symbol references from wbgenplus_pkg, so an empty package suffices. When external_uses.work.wbgenplus_pkg resolves through the registry, this stub is the canonical provider \u2014 explicit curator provenance, not a copy of any upstream artifact.", "license": "MIT", "language": "vhdl-2008", "library": "work", "source_url": "https://github.com/routertl/stubs.git", "tags": [ "sentinel", "stub", "wbgenplus" ], "role": "top", "library_deps": [], "created_at": "2026-05-07T13:05:03Z", "updated_at": "2026-05-07T15:04:29+02:00", "desc_source": "curator", "provides_packages": [ "wbgenplus_pkg" ], "top_modules": [ "wbgenplus_stub_sentinel" ] }, { "namespace": "stnolting", "name": "neo430", "latest": "master", "versions": [ "master" ], "description": ":information_source: Please check out the follow-up project: [The NEORV32 RISC-V Processor](https://github.com/stnolting/neorv32)", "license": "BSD-3-Clause", "language": "vhdl-2008", "library": "neo430", "source_url": "https://github.com/stnolting/neo430.git", "tags": [ "asynchronous", "axi4lite", "interface", "modulation", "peripheral", "processor", "receiver", "redundancy", "register", "sysconfig", "transmitter", "universal" ], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2021-11-23T08:13:21+01:00", "status": "deprecated-upstream", "successor": "stnolting/neorv32", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "readme", "external_uses": [ { "library": "iCE40UP", "package": "components" } ], "provides_packages": [ "neo430_application_image", "neo430_bootloader_image", "neo430_package" ], "top_ports": { "neo430_test": [ { "direction": "in", "name": "clk_i", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_ulogic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_ulogic_vector", "width": "07 downto 0" }, { "direction": "out", "name": "uart_txd_o", "type": "std_ulogic", "width": "" }, { "direction": "in", "name": "uart_rxd_i", "type": "std_ulogic", "width": "" } ], "neo430_top_avm": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "gpio_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "pwm_o", "type": "std_logic_vector", "width": "03 downto 0" }, { "direction": "out", "name": "freq_gen_o", "type": "std_logic_vector", "width": "02 downto 0" }, { "direction": "out", "name": "uart_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_miso_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_cs_o", "type": "std_logic_vector", "width": "05 downto 0" }, { "direction": "inout", "name": "twi_sda_io", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "twi_scl_io", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ext_irq_i", "type": "std_logic_vector", "width": "07 downto 0" }, { "direction": "out", "name": "ext_ack_o", "type": "std_logic_vector", "width": "07 downto 0" }, { "direction": "out", "name": "avm_address", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "avm_readdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "avm_writedata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "avm_byteenable", "type": "std_logic_vector", "width": "03 downto 0" }, { "direction": "out", "name": "avm_write", "type": "std_logic", "width": "" }, { "direction": "out", "name": "avm_read", "type": "std_logic", "width": "" }, { "direction": "in", "name": "avm_waitrequest", "type": "std_logic", "width": "" } ], "neo430_top_axi4lite": [ { "direction": "out", "name": "gpio_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "gpio_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "pwm_o", "type": "std_logic_vector", "width": "03 downto 0" }, { "direction": "out", "name": "freq_gen_o", "type": "std_logic_vector", "width": "02 downto 0" }, { "direction": "out", "name": "uart_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_miso_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_cs_o", "type": "std_logic_vector", "width": "05 downto 0" }, { "direction": "inout", "name": "twi_sda_io", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "twi_scl_io", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ext_irq_i", "type": "std_logic_vector", "width": "07 downto 0" }, { "direction": "out", "name": "ext_ack_o", "type": "std_logic_vector", "width": "07 downto 0" }, { "direction": "in", "name": "m_axi_aclk", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_aresetn", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_awaddr", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_awvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_awready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_awprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "out", "name": "m_axi_wdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_wstrb", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "m_axi_wvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_wready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_araddr", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "m_axi_arvalid", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_arready", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_arprot", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "m_axi_rdata", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "m_axi_rresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "m_axi_rvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_rready", "type": "std_logic", "width": "" }, { "direction": "in", "name": "m_axi_bresp", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "m_axi_bvalid", "type": "std_logic", "width": "" }, { "direction": "out", "name": "m_axi_bready", "type": "std_logic", "width": "" } ], "neo430_top_std_logic": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "gpio_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "gpio_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "pwm_o", "type": "std_logic_vector", "width": "03 downto 0" }, { "direction": "out", "name": "freq_gen_o", "type": "std_logic_vector", "width": "02 downto 0" }, { "direction": "out", "name": "uart_txd_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_miso_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_cs_o", "type": "std_logic_vector", "width": "05 downto 0" }, { "direction": "inout", "name": "twi_sda_io", "type": "std_logic", "width": "" }, { "direction": "inout", "name": "twi_scl_io", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_adr_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_we_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_sel_o", "type": "std_logic_vector", "width": "03 downto 0" }, { "direction": "out", "name": "wb_stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_cyc_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_ack_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "ext_irq_i", "type": "std_logic_vector", "width": "07 downto 0" }, { "direction": "out", "name": "ext_ack_o", "type": "std_logic_vector", "width": "07 downto 0" } ] }, "top_modules": [ "neo430_test", "neo430_top_avm", "neo430_top_axi4lite", "neo430_top_std_logic" ] }, { "namespace": "white-rabbit", "name": "wr-common", "latest": "master", "versions": [ "master" ], "description": "Shared internals required by every wr-cores subsystem \u2014 WRF (White Rabbit Fabric) primitives, DMTD (Digital Multi-Tap Delay) phase meters, pulse helpers, fabric mux/reg/loopback. Not a standalone install target; auto-pulled via external_uses by wr-ptp-core, wr-endpoint, wr-softpll-ng, wr-streamers, wr-mini-nic.", "license": "LGPL-2.1", "language": "vhdl-2008", "library": "wr", "source_url": "https://gitlab.cern.ch/white-rabbit/wr-cores.git", "tags": [ "controller", "deglitcher", "detect", "fabric", "loopback", "multi", "multiplexer", "period", "register", "source", "stamper", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-07T08:16:54Z", "updated_at": "2017-12-18T18:45:29+01:00", "desc_source": "curator", "external_uses": [ { "library": "work", "package": "gencores_pkg" }, { "library": "work", "package": "genram_pkg" }, { "library": "work", "package": "wb_irq_pkg" }, { "library": "work", "package": "wbgen2_pkg" }, { "library": "work", "package": "wbgenplus_pkg" }, { "library": "work", "package": "wishbone_pkg" }, { "library": "work", "package": "wr_transmission_wbgen2_pkg" } ], "provides_packages": [ "endpoint_pkg", "endpoint_private_pkg", "ep_wbgen2_pkg", "lbk_wbgen2_pkg", "wr_fabric_pkg" ], "top_ports": { "dmtd_phase_meas": [ { "direction": "in", "name": "rst_sys_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_dmtd_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_b_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_dmtd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "en_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "navg_i", "type": "std_logic_vector", "width": "11 downto 0" }, { "direction": "out", "name": "phase_meas_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "phase_meas_p_o", "type": "std_logic", "width": "" } ], "hpll_period_detect": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_fbck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_refclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_fbck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_sysclk_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_err_o", "type": "std_logic_vector", "width": "11 downto 0" }, { "direction": "out", "name": "freq_err_stb_p_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "hpll_fbcr_fd_gate_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": "hpll_fbcr_ferr_set_i", "type": "std_logic_vector", "width": "11 downto 0" } ], "multi_dmtd_with_deglitcher": [ { "direction": "in", "name": "rst_n_dmtdclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_sysclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_dmtd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_in_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "tag_o", "type": "std_logic_vector", "width": "g_counter_bits-1 downto 0" }, { "direction": "out", "name": "tag_stb_p_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "shift_en_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "shift_dir_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "deglitch_threshold_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "dbg_dmtdout_o", "type": "std_logic", "width": "" } ], "pulse_gen": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pulse_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "tm_time_valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "tm_tai_i", "type": "std_logic_vector", "width": "39 downto 0" }, { "direction": "in", "name": "tm_cycles_i", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "out", "name": "trig_ready_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "trig_tai_i", "type": "std_logic_vector", "width": "39 downto 0" }, { "direction": "in", "name": "trig_cycles_i", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "in", "name": "trig_valid_i", "type": "std_logic", "width": "" } ], "pulse_stamper": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pulse_a_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "tm_time_valid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "tm_tai_i", "type": "std_logic_vector", "width": "39 downto 0" }, { "direction": "in", "name": "tm_cycles_i", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "out", "name": "tag_tai_o", "type": "std_logic_vector", "width": "39 downto 0" }, { "direction": "out", "name": "tag_cycles_o", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "out", "name": "tag_valid_o", "type": "std_logic", "width": "" } ], "wb_fabric_sink": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "out", "name": "addr_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "data_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "dvalid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sof_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eof_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "error_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "bytesel_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dreq_i", "type": "std_logic", "width": "" } ], "wb_fabric_source": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "src_o", "type": "t_wrf_source_out", "width": "" }, { "direction": "in", "name": "addr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "data_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "dvalid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sof_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "eof_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "error_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bytesel_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dreq_o", "type": "std_logic", "width": "" } ], "wrf_loopback": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_sel_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "snk_adr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "snk_dat_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "snk_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "snk_stall_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_cyc_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_we_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_sel_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "src_adr_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "src_dat_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "src_ack_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_stall_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_cyc_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_stb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_we_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_sel_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "wb_adr_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "in", "name": "wb_dat_i", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_dat_o", "type": "std_logic_vector", "width": "31 downto 0" }, { "direction": "out", "name": "wb_ack_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "wb_stall_o", "type": "std_logic", "width": "" } ], "xwb_fabric_sink": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "out", "name": "addr_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "data_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "dvalid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sof_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "eof_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "error_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "bytesel_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "dreq_i", "type": "std_logic", "width": "" } ], "xwb_fabric_source": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "src_o", "type": "t_wrf_source_out", "width": "" }, { "direction": "in", "name": "addr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "data_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "dvalid_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sof_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "eof_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "error_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "bytesel_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dreq_o", "type": "std_logic", "width": "" } ], "xwrf_mux": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ep_src_o", "type": "t_wrf_source_out", "width": "" }, { "direction": "in", "name": "ep_src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "ep_snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "in", "name": "ep_snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "mux_src_o", "type": "t_wrf_source_out_array", "width": "g_muxed_ports-1 downto 0" }, { "direction": "in", "name": "mux_src_i", "type": "t_wrf_source_in_array", "width": "g_muxed_ports-1 downto 0" }, { "direction": "out", "name": "mux_snk_o", "type": "t_wrf_sink_out_array", "width": "g_muxed_ports-1 downto 0" }, { "direction": "in", "name": "mux_snk_i", "type": "t_wrf_sink_in_array", "width": "g_muxed_ports-1 downto 0" }, { "direction": "in", "name": "mux_class_i", "type": "t_wrf_mux_class", "width": "g_muxed_ports-1 downto 0" } ], "xwrf_reg": [ { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "in", "name": "src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "src_o", "type": "t_wrf_source_out", "width": "" } ] }, "top_modules": [ "dmtd_phase_meas", "hpll_period_detect", "multi_dmtd_with_deglitcher", "pulse_gen", "pulse_stamper", "wb_fabric_sink", "wb_fabric_source", "wrf_loopback", "xwb_fabric_sink", "xwb_fabric_source", "xwrf_mux", "xwrf_reg" ] }, { "namespace": "white-rabbit", "name": "wr-eca", "latest": "master", "versions": [ "master" ], "description": "ECA \u2014 Event Conditional Action timing controller. Hardware action scheduler that triggers outputs on absolute timestamp matches with sub-ns precision. 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"eca_internals_pkg", "eca_pkg", "eca_queue_auto_pkg", "eca_tlu_auto_pkg" ], "top_ports": { "eca_ac_wbm": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_ref_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "channel_i", "type": "t_channel", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_sys_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "master_i", "type": "t_wishbone_master_in", "width": "" } ], "eca_bitonic": [ { "direction": "in", "name": "clk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": 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"t_wishbone_master_out", "width": "" } ] }, "top_modules": [ "eca_ac_wbm", "eca_bitonic", "eca_compact", "eca_fifo", "eca_queue", "eca_scubus_channel", "eca_tlu", "eca_wb_event", "wr_eca" ] }, { "namespace": "white-rabbit", "name": "wr-endpoint", "latest": "master", "versions": [ "master" ], "description": "1G WR Endpoint \u2014 Gigabit Ethernet MAC + 1000Base-X PCS + PTP timestamping unit. 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"std_logic_vector", "width": "48 - 1 downto 0" }, { "direction": "out", "name": "rtu_rq_dmac_o", "type": "std_logic_vector", "width": "48 - 1 downto 0" }, { "direction": "out", "name": "rtu_rq_vid_o", "type": "std_logic_vector", "width": "12 - 1 downto 0" }, { "direction": "out", "name": "rtu_rq_has_vid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rtu_rq_prio_o", "type": "std_logic_vector", "width": "3 - 1 downto 0" }, { "direction": "out", "name": "rtu_rq_has_prio_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "wb_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "wb_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "pfilter_pclass_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "pfilter_drop_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pfilter_done_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "fc_tx_pause_req_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "fc_tx_pause_delay_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "fc_tx_pause_ready_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "fc_rx_pause_start_p_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "fc_rx_pause_quanta_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "fc_rx_pause_prio_mask_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "out", "name": "fc_rx_buffer_occupation_o", "type": "std_logic_vector", "width": "7 downto 0" }, { "direction": "in", "name": "inject_req_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "inject_ready_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "inject_packet_sel_i", "type": "std_logic_vector", "width": "2 downto 0" }, { "direction": "in", "name": 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"nice_dbg_o", "type": "t_dbg_ep", "width": "" } ] }, "top_modules": [ "ep_flow_control", "ep_rmon_counters", "ep_rx_bypass_queue", "ep_shift_reg", "ep_tx_framer", "xwr_endpoint" ] }, { "namespace": "white-rabbit", "name": "wr-mini-nic", "latest": "master", "versions": [ "master" ], "description": "Mini-NIC \u2014 minimal Wishbone-mastered Ethernet NIC for the embedded LM32 SoftCPU running the PTP stack. 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}, { "direction": "in", "name": "phy_sfp_los_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "phy_sfp_tx_disable_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "phy8_o", "type": "t_phy_8bits_from_wrc", "width": "" }, { "direction": "in", "name": "phy8_i", "type": "t_phy_8bits_to_wrc", "width": "" }, { "direction": "out", "name": "phy16_o", "type": "t_phy_16bits_from_wrc", "width": "" }, { "direction": "in", "name": "phy16_i", "type": "t_phy_16bits_to_wrc", "width": "" }, { "direction": "out", "name": "led_act_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "led_link_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "scl_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sda_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sda_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sfp_scl_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sfp_scl_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sfp_sda_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sfp_sda_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sfp_det_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "btn1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "btn2_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_sclk_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_ncs_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "spi_mosi_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "spi_miso_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "uart_rxd_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "uart_txd_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "owr_pwren_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "owr_en_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "owr_i", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "in", "name": "slave_i", "type": "t_wishbone_slave_in", "width": "" }, { "direction": "out", "name": "slave_o", "type": "t_wishbone_slave_out", "width": "" }, { "direction": "out", "name": "aux_master_o", "type": "t_wishbone_master_out", "width": "" }, { "direction": "in", "name": "aux_master_i", "type": "t_wishbone_master_in", "width": "" }, { "direction": "out", "name": "wrf_src_o", "type": "t_wrf_source_out", "width": "" }, { "direction": "in", "name": "wrf_src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "wrf_snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "in", "name": "wrf_snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "timestamps_o", "type": "t_txtsu_timestamp", "width": "" }, { "direction": "in", "name": "timestamps_ack_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "abscal_txts_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "abscal_rxts_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "fc_tx_pause_req_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "fc_tx_pause_delay_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "fc_tx_pause_ready_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "tm_link_up_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "tm_dac_value_o", "type": "std_logic_vector", "width": "23 downto 0" }, { "direction": "out", "name": "tm_dac_wr_o", "type": "std_logic_vector", "width": "g_aux_clks-1 downto 0" }, { "direction": "in", "name": "tm_clk_aux_lock_en_i", "type": "std_logic_vector", "width": "g_aux_clks-1 downto 0" }, { "direction": "out", "name": "tm_clk_aux_locked_o", "type": "std_logic_vector", "width": "g_aux_clks-1 downto 0" }, { "direction": "out", "name": "tm_time_valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "tm_tai_o", "type": "std_logic_vector", "width": "39 downto 0" }, { "direction": "out", "name": "tm_cycles_o", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "out", "name": "pps_csync_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pps_p_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "pps_led_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rst_aux_n_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "aux_diag_i", "type": "t_generic_word_array", "width": "g_diag_ro_size-1 downto 0" }, { "direction": "out", "name": "aux_diag_o", "type": "t_generic_word_array", "width": "g_diag_rw_size-1 downto 0" }, { "direction": "out", "name": "link_ok_o", "type": "std_logic", "width": "" } ] }, "top_modules": [ "xwr_core" ] }, { "namespace": "white-rabbit", "name": "wr-softpll-ng", "latest": "master", "versions": [ "master" ], "description": "SoftPLL-NG \u2014 software-controlled PLL for sub-nanosecond clock recovery. Carrier-grade clock-domain alignment using DDMTD (Dual-Mixer Time-to-Digital) phase detection plus bang-bang + period-detect digital PI loops. The clock-recovery heart of the WR system.", "license": "LGPL-2.1", "language": "vhdl-2008", "library": "wr", "source_url": "https://gitlab.cern.ch/white-rabbit/wr-cores.git", "tags": [ "aligner", "bangbang", "bus", "detect", "ng", "pd", "period", "slave", "softpll", "spll", "wishbone", "xwr" ], "role": "top", "library_deps": [], "created_at": "2026-05-07T08:16:54Z", "updated_at": "2017-12-18T18:45:29+01:00", "desc_source": "curator", "external_uses": [ { "library": "work", "package": "gencores_pkg" }, { "library": "work", "package": "genram_pkg" }, { "library": "work", "package": "wb_irq_pkg" }, { "library": "work", "package": "wbgen2_pkg" }, { "library": "work", "package": "wbgenplus_pkg" }, { "library": "work", "package": "wishbone_pkg" }, { "library": "work", "package": "wr_transmission_wbgen2_pkg" } ], "provides_packages": [ "softpll_pkg", "spll_wbgen2_pkg" ], "top_ports": { "spll_bangbang_pd": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_fb_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_refclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_fbck_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_sysclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cfg_div_ref_i", "type": "std_logic_vector", "width": "5 downto 0" }, { "direction": "in", "name": "cfg_div_fb_i", "type": "std_logic_vector", "width": "5 downto 0" }, { "direction": "in", "name": "cfg_gating_i", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "in", "name": "sync_p_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "sync_en_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "sync_done_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "err_wrap_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "err_o", "type": "std_logic_vector", "width": "g_error_bits-1 downto 0" }, { "direction": "out", "name": "err_stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "ref_present_o", "type": "std_logic", "width": "" } ], "spll_period_detect": [ { "direction": "in", "name": "clk_ref_i", "type": "std_logic_vector", "width": "g_num_ref_inputs-1 downto 0" }, { "direction": "in", "name": "clk_dmtd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_dmtdclk_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_sysclk_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "freq_err_o", "type": "std_logic_vector", "width": "11 downto 0" }, { "direction": "out", "name": "freq_err_stb_p_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "in_sel_i", "type": "std_logic_vector", "width": "4 downto 0" } ], "xwr_softpll_ng": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_sys_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_ref_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_ext_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_dmtd_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ref_i", "type": "std_logic_vector", "width": "g_num_ref_inputs-1 downto 0" }, { "direction": "in", "name": "clk_fb_i", "type": "std_logic_vector", "width": "g_num_outputs-1 downto 0" }, { "direction": "in", "name": "clk_dmtd_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ext_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ext_mul_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ext_mul_locked_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "clk_ext_stopped_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "clk_ext_rst_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_csync_p1_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "pps_ext_a_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dac_dmtd_data_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "dac_dmtd_load_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "dac_out_data_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "dac_out_sel_o", "type": "std_logic_vector", "width": "3 downto 0" }, { "direction": "out", "name": "dac_out_load_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "out_enable_i", "type": "std_logic_vector", "width": "g_num_outputs-1 downto 0" }, { "direction": "out", "name": "out_locked_o", "type": "std_logic_vector", "width": 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Drop-buffer, escape detection/insertion, statistics counters, Wishbone-mapped configuration.", "license": "LGPL-2.1", "language": "vhdl-2008", "library": "wr", "source_url": "https://gitlab.cern.ch/white-rabbit/wr-cores.git", "tags": [ "buffer", "detector", "dropping", "escape", "inserter", "receive", "receiver", "streamer", "streamers", "transmit", "transmitter", "wishbone" ], "role": "top", "library_deps": [], "created_at": "2026-05-07T08:16:54Z", "updated_at": "2017-12-18T18:45:29+01:00", "desc_source": "curator", "external_uses": [ { "library": "work", "package": "gencores_pkg" }, { "library": "work", "package": "genram_pkg" }, { "library": "work", "package": "wb_irq_pkg" }, { "library": "work", "package": "wbgen2_pkg" }, { "library": "work", "package": "wbgenplus_pkg" }, { "library": "work", "package": "wishbone_pkg" }, { "library": "work", "package": "wr_transmission_wbgen2_pkg" } ], "provides_packages": [ "endpoint_pkg", "softpll_pkg", "streamers_pkg", "streamers_priv_pkg", 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"direction": "out", "name": "rx_lost_blocks_p1_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rx_lost_frames_p1_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rx_lost_frames_cnt_o", "type": "std_logic_vector", "width": "14 downto 0" }, { "direction": "out", "name": "rx_latency_o", "type": "std_logic_vector", "width": "27 downto 0" }, { "direction": "out", "name": "rx_latency_valid_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "rx_frame_p1_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cfg_mac_local_i", "type": "std_logic_vector", "width": "47 downto 0" }, { "direction": "in", "name": "cfg_mac_remote_i", "type": "std_logic_vector", "width": "47 downto 0" }, { "direction": "in", "name": "cfg_ethertype_i", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "in", "name": "cfg_accept_broadcasts_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cfg_filter_remote_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cfg_fixed_latency_i", "type": "std_logic_vector", "width": "27 downto 0" } ], "tx_streamer": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_dat_o", "type": "std_logic_vector", "width": "15 downto 0" }, { "direction": "out", "name": "src_adr_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "src_sel_o", "type": "std_logic_vector", "width": "1 downto 0" }, { "direction": "out", "name": "src_cyc_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_stb_o", "type": "std_logic", "width": "" }, { "direction": "out", "name": "src_we_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_stall_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_ack_i", "type": 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"name": "tx_frame_p1_o", "type": "std_logic", "width": "" }, { "direction": "in", "name": "cfg_mac_local_i", "type": "std_logic_vector", "width": "47 downto 0" }, { "direction": "in", "name": "cfg_mac_target_i", "type": "std_logic_vector", "width": "47 downto 0" }, { "direction": "in", "name": "cfg_ethertype_i", "type": "std_logic_vector", "width": "15 downto 0" } ], "xwr_streamers": [ { "direction": "in", "name": "clk_sys_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "rst_n_i", "type": "std_logic", "width": "" }, { "direction": "in", "name": "src_i", "type": "t_wrf_source_in", "width": "" }, { "direction": "out", "name": "src_o", "type": "t_wrf_source_out", "width": "" }, { "direction": "in", "name": "snk_i", "type": "t_wrf_sink_in", "width": "" }, { "direction": "out", "name": "snk_o", "type": "t_wrf_sink_out", "width": "" }, { "direction": "in", "name": "tx_data_i", "type": "std_logic_vector", "width": "g_tx_streamer_params.data_width-1 downto 0" }, { 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], "description": "TBI (Ten-Bit Interface) PHY adapter + 8b/10b coder. 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"direction": "in", "name": "S_AXI_AWQOS", "type": "wire", "width": "[3:0]" }, { "direction": "in", "name": "S_AXI_WVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_WREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_WDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_WSTRB", "type": "wire", "width": "[C_AXI_DATA_WIDTH/8-1:0]" }, { "direction": "in", "name": "S_AXI_WLAST", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BID", "type": "wire", "width": "[C_AXI_ID_WIDTH-1:0]" }, { "direction": "out", "name": "S_AXI_BRESP", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "S_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": 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"name": "M_AXI_AWVALID", "type": "wire", "width": "[NS-1:0]" }, { "direction": "out", "name": "M_AXI_AWADDR", "type": "wire", "width": "[C_AXI_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "M_AXI_AWPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "out", "name": "M_AXI_WDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "M_AXI_WSTRB", "type": "wire", "width": "[C_AXI_DATA_WIDTH/8-1:0]" }, { "direction": "in", "name": "M_AXI_BRESP", "type": "wire", "width": "[NS*2-1:0]" }, { "direction": "out", "name": "M_AXI_ARVALID", "type": "wire", "width": "[NS-1:0]" }, { "direction": "out", "name": "M_AXI_ARADDR", "type": "wire", "width": "[C_AXI_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "M_AXI_ARPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "in", "name": "M_AXI_RDATA", "type": "wire", "width": "[NS*C_AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "M_AXI_RRESP", "type": "wire", "width": "[NS*2-1:0]" } ] } }, { "namespace": "zipcpu", "name": "axilempty", "latest": "master", "versions": [ "master" ], "description": "Implements an AXI-lite slave interface that responds to read/write transactions with empty responses.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:58Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "axilempty": [ { "direction": "in", "name": "S_AXI_ACLK", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_ARESETN", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_AWVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_AWREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_WVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_WREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BRESP", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "S_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_RVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_RREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_RDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "S_AXI_RRESP", "type": "wire", "width": "[1:0]" } ] } }, { "namespace": "zipcpu", "name": "axilfetch", "latest": "master", "versions": [ "master" ], "description": "Axilfetch IP core with ready/valid handshake and configurable parameters", "license": "GPL-3.0-or-later", "language": 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{ "direction": "in", "name": "S_AXI_WSTRB", "type": "wire", "width": "[C_AXI_DATA_WIDTH/8-1:0]" }, { "direction": "out", "name": "S_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BRESP", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "S_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_ARADDR", "type": "wire", "width": "[C_AXI_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_ARPROT", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "S_AXI_RVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_RREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_RDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "S_AXI_RRESP", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "o_gpio", "type": "wire", "width": "[NOUT-1:0]" }, { "direction": "in", "name": "i_gpio", "type": "wire", "width": "[((NIN>0) ? (NIN-1):0):0]" }, { "direction": "out", "name": "o_int", "type": "wire", "width": "" }, { "direction": "in", "name": "registers", "type": "wire", "width": "" }, { "direction": "in", "name": "prior_data", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "new_data", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "wstrb", "type": "wire", "width": "[C_AXI_DATA_WIDTH/8-1:0]" } ] } }, { "namespace": "zipcpu", "name": "axilite2axi", "latest": "master", "versions": [ "master" ], "description": "Converts AXI4-Lite slave interface to full AXI4 master interface with configurable ID and data width.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": 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"wire", "width": "" }, { "direction": "out", "name": "S_AXI_BRESP", "type": "wire", "width": "[2-1:0]" }, { "direction": "in", "name": "S_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_ARADDR", "type": "wire", "width": "[C_AXI_ADDR_WIDTH-1:0]" }, { "direction": "in", "name": "S_AXI_ARPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "out", "name": "S_AXI_RVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_RREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_RDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "out", "name": "S_AXI_RRESP", "type": "wire", "width": "[2-1:0]" }, { "direction": "out", "name": "M_AXI_AWVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_AWREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_AWID", "type": "wire", "width": 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"M_AXI_WSTRB", "type": "wire", "width": "[C_AXI_DATA_WIDTH/8-1:0]" }, { "direction": "out", "name": "M_AXI_WLAST", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_BID", "type": "wire", "width": "[C_AXI_ID_WIDTH-1:0]" }, { "direction": "in", "name": "M_AXI_BRESP", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "M_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_ARID", "type": "wire", "width": "[C_AXI_ID_WIDTH-1:0]" }, { "direction": "out", "name": "M_AXI_ARADDR", "type": "wire", "width": "[C_AXI_ADDR_WIDTH-1:0]" }, { "direction": "out", "name": "M_AXI_ARLEN", "type": "wire", "width": "[8-1:0]" }, { "direction": "out", "name": "M_AXI_ARSIZE", "type": "wire", "width": "[3-1:0]" }, { "direction": "out", "name": "M_AXI_ARBURST", "type": "wire", "width": "[2-1:0]" }, { "direction": "out", "name": "M_AXI_ARLOCK", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_ARCACHE", "type": "wire", "width": "[4-1:0]" }, { "direction": "out", "name": "M_AXI_ARPROT", "type": "wire", "width": "[3-1:0]" }, { "direction": "out", "name": "M_AXI_ARQOS", "type": "wire", "width": "[4-1:0]" }, { "direction": "in", "name": "M_AXI_RVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_RREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_RID", "type": "wire", "width": "[C_AXI_ID_WIDTH-1:0]" }, { "direction": "in", "name": "M_AXI_RDATA", "type": "wire", "width": "[C_AXI_DATA_WIDTH-1:0]" }, { "direction": "in", "name": "M_AXI_RLAST", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_RRESP", "type": "wire", "width": "[2-1:0]" } ] } }, { "namespace": "zipcpu", "name": "axilsafety", "latest": "master", "versions": [ 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"name": "S_AXI_AWADDR", "type": "wire", "width": "[AW-1:0]" }, { "direction": "in", "name": "S_AXI_AWPROT", "type": "wire", "width": "[2:0]" }, { "direction": "in", "name": "S_AXI_WVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_WREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_WDATA", "type": "wire", "width": "[DW-1:0]" }, { "direction": "in", "name": "S_AXI_WSTRB", "type": "wire", "width": "[DW/8-1:0]" }, { "direction": "out", "name": "S_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_BRESP", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "S_AXI_ARVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_ARREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_ARADDR", "type": "wire", "width": "[AW-1:0]" }, { "direction": "in", "name": "S_AXI_ARPROT", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "S_AXI_RVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "S_AXI_RREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "S_AXI_RDATA", "type": "wire", "width": "[DW-1:0]" }, { "direction": "out", "name": "S_AXI_RRESP", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "M_AXI_AWVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_AWREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_AWADDR", "type": "wire", "width": "[AW-1:0]" }, { "direction": "out", "name": "M_AXI_AWPROT", "type": "wire", "width": "[2:0]" }, { "direction": "out", "name": "M_AXI_WVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_WREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_WDATA", "type": "wire", "width": "[DW-1:0]" }, { "direction": "out", "name": "M_AXI_WSTRB", "type": "wire", "width": "[DW/8-1:0]" }, { "direction": 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"direction": "out", "name": "M_AXI_WVALID", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_WREADY", "type": "wire", "width": "" }, { "direction": "in", "name": "M_AXI_BID", "type": "wire", "width": "[IW-1 : 0]" }, { "direction": "in", "name": "M_AXI_BRESP", "type": "wire", "width": "[1 : 0]" }, { "direction": "in", "name": "M_AXI_BVALID", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_BREADY", "type": "wire", "width": "" }, { "direction": "out", "name": "M_AXI_ARID", "type": "wire", "width": "[IW-1 : 0]" }, { "direction": "out", "name": "M_AXI_ARADDR", "type": "wire", "width": "[AW-1 : 0]" }, { "direction": "out", "name": "M_AXI_ARLEN", "type": "wire", "width": "[7 : 0]" }, { "direction": "out", "name": "M_AXI_ARSIZE", "type": "wire", "width": "[2 : 0]" }, { "direction": "out", "name": "M_AXI_ARBURST", "type": "wire", "width": "[1 : 0]" }, { "direction": "out", "name": "M_AXI_ARLOCK", "type": "wire", "width": "" }, { "direction": "out", "name": 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"o_wb_data", "type": "wire", "width": "[31:0]" }, { "direction": "out", "name": "o_spi_cs_n", "type": "wire", "width": "" }, { "direction": "in", "name": "i_spi_miso", "type": "wire", "width": "" }, { "direction": "in", "name": "B", "type": "wire", "width": "[7:0]" } ] } }, { "namespace": "zipcpu", "name": "wbc2pipeline", "latest": "master", "versions": [ "master" ], "description": "Converts Wishbone classic protocol transactions to pipelined protocol transactions with configurable address and data widths.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "wbc2pipeline": [ { "direction": "in", "name": "i_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_scyc", 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"type": "wire", "width": "" }, { "direction": "in", "name": "i_mack", "type": "wire", "width": "" }, { "direction": "in", "name": "i_mdata", "type": "wire", "width": "[DW-1:0]" }, { "direction": "in", "name": "i_merr", "type": "wire", "width": "" } ] } }, { "namespace": "zipcpu", "name": "wbdown", "latest": "master", "versions": [ "master" ], "description": "Converts wide Wishbone bus transactions to narrower bus transactions with address and data width adaptation.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "wbdown": [ { "direction": "in", "name": "i_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_wcyc", "type": "wire", "width": "" }, { "direction": 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"i_wdata", "type": "wire", "width": "[WIDE_DW-1:0]" }, { "direction": "in", "name": "i_werr", "type": "wire", "width": "" } ] } }, { "namespace": "zipcpu", "name": "wbxbar", "latest": "master", "versions": [ "master" ], "description": "Crossbar switch", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "ports", "top_ports": { "wbxbar": [ { "direction": "in", "name": "ports", "type": "wire", "width": "" }, { "direction": "in", "name": "i_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_mcyc", "type": "wire", "width": "[NM-1:0]" }, { "direction": "in", "name": "i_maddr", "type": "wire", "width": "[NM*AW-1:0]" }, { "direction": "in", "name": "i_mdata", "type": "wire", "width": "[NM*DW-1:0]" }, { "direction": "in", "name": "i_msel", "type": "wire", "width": "[NM*DW/8-1:0]" }, { "direction": "out", "name": "o_mstall", "type": "wire", "width": "[NM-1:0]" }, { "direction": "out", "name": "o_mack", "type": "wire", "width": "[NM-1:0]" }, { "direction": "out", "name": "o_mdata", "type": "wire", "width": "[NM*DW-1:0]" }, { "direction": "out", "name": "o_merr", "type": "wire", "width": "[NM-1:0]" }, { "direction": "out", "name": "o_scyc", "type": "wire", "width": "[NS-1:0]" }, { "direction": "out", "name": "o_saddr", "type": "wire", "width": "[NS*AW-1:0]" }, { "direction": "out", "name": "o_sdata", "type": "wire", "width": "[NS*DW-1:0]" }, { "direction": "out", "name": "o_ssel", "type": "wire", "width": "[NS*DW/8-1:0]" }, { "direction": "in", "name": "i_sstall", "type": "wire", "width": "[NS-1:0]" }, { "direction": "in", "name": "i_sdata", "type": "wire", "width": "[NS*DW-1:0]" }, { "direction": "in", "name": "i_serr", "type": "wire", "width": "[NS-1:0]" } ] } }, { "namespace": "zipcpu", "name": "wbxclk", "latest": "master", "versions": [ "master" ], "description": "Wishbone bus bridge that synchronizes transactions from one clock domain to another using a FIFO buffer.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/wb2axip.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:59Z", "updated_at": "2026-03-10T13:49:52-04:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "wbxclk": [ { "direction": "in", "name": "i_wb_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_wb_cyc", "type": "wire", "width": "" }, { "direction": "in", "name": "i_wb_addr", "type": "wire", "width": "[(AW-1):0]" }, { "direction": "in", "name": "i_wb_data", "type": "wire", "width": "[(DW-1):0]" }, { "direction": "in", "name": "i_wb_sel", "type": "wire", "width": "[(DW/8-1):0]" }, { "direction": "out", "name": "o_wb_stall", "type": "wire", "width": "" }, { "direction": "out", "name": "o_wb_ack", "type": "wire", "width": "" }, { "direction": "out", "name": "o_wb_data", "type": "wire", "width": "[(DW-1):0]" }, { "direction": "out", "name": "o_wb_err", "type": "wire", "width": "" }, { "direction": "in", "name": "i_xclk_clk", "type": "wire", "width": "" }, { "direction": "out", "name": "o_xclk_cyc", "type": "wire", "width": "" }, { "direction": "out", "name": "o_xclk_stb", "type": "wire", "width": "" }, { "direction": "out", "name": "o_xclk_we", "type": "wire", "width": "" }, { "direction": "out", "name": "o_xclk_addr", "type": "wire", "width": "[(AW-1):0]" }, { "direction": "out", "name": "o_xclk_data", "type": "wire", "width": "[(DW-1):0]" }, { "direction": "out", "name": "o_xclk_sel", "type": "wire", "width": "[(DW/8-1):0]" }, { "direction": "in", "name": "i_xclk_stall", "type": "wire", "width": "" }, { "direction": "in", "name": "i_xclk_ack", "type": "wire", "width": "" }, { "direction": "in", "name": "i_xclk_data", "type": "wire", "width": "[(DW-1):0]" }, { "direction": "in", "name": "i_xclk_err", "type": "wire", "width": "" } ] } }, { "namespace": "zipcpu", "name": "xddrck", "latest": "master", "versions": [ "master" ], "description": "Multiplexes two input signals based on clock selection to produce a single output pin.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/qspiflash.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:58Z", "updated_at": "2021-01-25T11:57:49-05:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "xddrck": [ { "direction": "in", "name": "i_clk", "type": "wire", "width": "[1:0]" }, { "direction": "in", "name": "i_v", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "o_pin", "type": "wire", "width": "" } ] } }, { "namespace": "zipcpu", "name": "xioddr", "latest": "master", "versions": [ "master" ], "description": "Bidirectional DDR I/O buffer with output enable control for dual-rate data transmission.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/qspiflash.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:58Z", "updated_at": "2021-01-25T11:57:49-05:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "xioddr": [ { "direction": "in", "name": "i_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_v", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "o_v", "type": "wire", "width": "[1:0]" }, { "direction": "inout", "name": "io_pin", "type": "wire", "width": "" } ] } }, { "namespace": "zipcpu", "name": "xoddr", "latest": "master", "versions": [ "master" ], "description": "Outputs a single pin signal controlled by a 2-bit input, clocked at the input clock rate.", "license": "GPL-3.0-or-later", "language": "verilog", "library": "work", "source_url": "https://github.com/ZipCPU/qspiflash.git", "tags": [], "role": "top", "library_deps": [], "created_at": "2026-05-05T07:09:58Z", "updated_at": "2021-01-25T11:57:49-05:00", "health_tier": "bronze", "last_verified_at": "2026-05-05", "desc_source": "preserved", "top_ports": { "xoddr": [ { "direction": "in", "name": "i_clk", "type": "wire", "width": "" }, { "direction": "in", "name": "i_v", "type": "wire", "width": "[1:0]" }, { "direction": "out", "name": "o_pin", "type": "wire", "width": "" } ] } } ]